Synchronous Rectifier vs Schottky: USB-PD Application Fit

Overview of Technical Issues:

In USB-PD secondary-side rectification, Schottky diodes create harmful conduction losses that dissipate power as heat, reducing conversion efficiency especially at low output voltages; meanwhile, synchronous FET rectifiers offer lower conduction resistance but suffer from insufficient turn-off timing control, causing reverse conduction during switching transitions that negates efficiency gains—the goal is to achieve optimized rectification efficiency while ensuring reliable turn-off timing in the USB-PD power delivery topology.

Solution directions generated for this problem

Problem Direction 1 :

ImproveTurn-off timing control precision
VS
ConstraintSwitching transition energy loss

Inspiration 1 : Cross-domain reference

Application Principle: #19 Periodic action
Cross-domain applicability Assess applicability
Welding power supply with digital control of duty cycle
Innovative Solution Refine solution

Load-adaptive dual-mode gate drive with cycle-by-cycle switching speed modulation

Adaptive gate drive switches between modes based on load
How to solve :
  • Install fast comparator (response time <5ns) monitoring output current
  • threshold set at 2.5A distinguishes light/heavy load zones
  • Light load mode (I<2.5A): gate driver uses 15Ω series resistance, 80ns dead-time, gentle slew rate 2V/ns — switching loss 0.55W, reverse conduction negligible
  • Heavy load mode (I≥2.5A): gate driver bypasses resistor via MOSFET switch, 20ns dead-time, fast slew rate 8V/ns — prevents reverse conduction with <10ns precision, switching loss 1.15W only during high-current cycles
Expected Effect : Average switching loss 0.65W at mixed load; timing precision <10ns when critical; efficiency >95% across 5-20V USB-PD range
Risk Control :
  • comparator propagation delay variation ±3ns affects mode transition accuracy
  • gate driver bypass MOSFET requires Rds(on)<0.5Ω to avoid voltage drop
  • load current threshold calibration needed per unit for ±0.2A tolerance

Problem Direction 2 :

ImproveConversion efficiency
VS
ConstraintControl circuit complexity

Inspiration 1 : Cross-domain reference

Application Principle: #1 Segmentation
Cross-domain applicability Assess applicability
Methods and equipment for encoding/decoding video signals
Innovative Solution Refine solution

Voltage-segmented hybrid rectification architecture for USB-PD efficiency optimization

Divide USB-PD voltage range into distinct segments with optimized rectification topology per segment
How to solve :
  • Implement dual-path rectification: Schottky diodes (MBRS340T3G, 0.5V drop) for 12V-20V outputs where relative loss is 2.5-4.2%
  • synchronous MOSFETs (Si7336ADP, Rds(on)=18mΩ) with fixed 60ns dead-time for 5V-9V outputs where conduction dominates
  • Use voltage-threshold switching via single comparator (LMV331, 1.2V reference) to select rectification path based on output voltage—no adaptive timing circuits needed, adds only 4 components (comparator, 2 resistors, 1 MOSFET switch)
  • Configure fixed gate drive parameters per segment: 5V-9V path uses 12V gate drive with 3A peak current achieving 25ns rise/fall time
  • 12V-20V path bypasses FET entirely, eliminating gate charge loss of 0.8W
Expected Effect : Efficiency >96% at 5V/3A, >94% at 20V/3A; component count +4 vs baseline Schottky, -11 vs adaptive synchronous; BOM cost +8% vs Schottky, -22% vs adaptive
Risk Control :
  • voltage threshold drift ±50mV over temperature
  • path switching transient causing 20-30mV output ripple
  • Schottky reverse leakage at high temperature

Problem Direction 3 :

ImproveSwitching transition energy loss
VS
ConstraintMust not deteriorate

Inspiration 1 : Cross-domain reference

Application Principle: #10 Preliminary action
Cross-domain applicability Assess applicability
Switch control circuit and converter including the same
Innovative Solution Refine solution

Pre-staged gate voltage reservoir for loss-decoupled synchronous rectification

Pre-charge gate to intermediate voltage before critical switching event
How to solve :
  • Install a dual-stage gate drive circuit with 47µF reservoir capacitor pre-charged to 8V during non-critical phase (100-150ns before turn-off), consuming 0.25W at 5kHz pre-charge rate
  • Deploy fast discharge path using 0.5Ω gate resistor activated by comparator detecting drain-source voltage ≥90% final value, delivering final 4V in <20ns with 0.35W instantaneous loss
  • Implement body-diode voltage monitor (threshold 0.65V) triggering stage-two discharge, achieving <10ns turn-off precision with total switching loss 0.6W versus 1.2W baseline
Expected Effect : Switching loss reduced 50% to 0.6W; timing precision <10ns; efficiency >95% at 5V-20V USB-PD range
Risk Control :
  • reservoir capacitor ESR variation affecting pre-charge consistency
  • comparator propagation delay exceeding 8ns under temperature drift
  • gate resistor tolerance causing turn-off time scatter ±5ns

Problem Direction 4 :

ImproveTurn-off timing control precision
VS
ConstraintControl circuit complexity

Inspiration 1 : Cross-domain reference

Application Principle: #26 Copying
Cross-domain applicability Assess applicability
Semiconductor memory
Innovative Solution Refine solution

Body-diode voltage replica sensing for synchronous rectifier turn-off control

Use replica FET to mirror body-diode conduction
How to solve :
  • Install a replica synchronous FET (1/100 scale of main FET) in parallel with main rectifier, sharing gate drive signal but with isolated drain connection to a voltage divider network (two 10kΩ resistors)
  • When reverse conduction begins, replica body-diode conducts at identical 0.7V threshold, generating a voltage drop across the divider that triggers a single comparator (LM393, 1.3μs response) to immediately shut off both FETs
  • Replica scaling factor 1:100 ensures negligible power loss (<50mW) while maintaining identical electrical characteristics — gate threshold voltage matched within ±50mV, body-diode forward voltage within ±30mV across -40°C to +125°C
Expected Effect : Timing precision <8ns; component count +4 (replica FET, comparator, 2 resistors); BOM cost +8%; efficiency >95.5% at 5V output
Risk Control :
  • replica FET thermal tracking deviation >±5°C
  • comparator propagation delay variation ±15ns across temperature
  • voltage divider resistor tolerance causing false triggering
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