TVS Diode Array Design for Multi-Voltage Power Sequencing

Overview of Technical Issues:

During multi-voltage power sequencing, the TVS diode array creates harmful cross-conduction paths between power rails activating at different times, causing current leakage from energized rails to unpowered domains, voltage droop, and potential latch-up in load circuits; the goal is to achieve reliable transient protection across all rails while maintaining isolation integrity throughout the entire power-up and power-down sequence.

Solution directions generated for this problem

Problem Direction 1 :

ImproveInter-rail isolation impedance
VS
ConstraintTransient clamping response time

Inspiration 1 : Cross-domain reference

Application Principle: #19 Periodic action
Cross-domain applicability Assess applicability
Therapeutic polymeric nanoparticles and methods of making and using same
Innovative Solution Refine solution

Time-division multiplexed TVS protection with nanosecond duty cycling

Alternate TVS between isolation and protection modes at high frequency to maintain effective fast response
How to solve :
  • Implement 100MHz duty-cycled switching where TVS path remains open (>10kΩ) for 9.5ns and closes (<0.5Ω) for 0.5ns per 10ns cycle, providing 95% time-averaged isolation while capturing transients in 0.5ns windows
  • Use GaN HEMT switches (EPC2001 or equivalent, Ron=6mΩ, Qg=1.4nC) driven by 5V gate pulses at 100MHz from Si5351 clock generator, achieving <500ps transition time and maintaining <1ns worst-case transient response
  • Deploy edge-triggered latch circuit using 74AUP1G74 D-flip-flop that detects dV/dt >0.5V/ns during closed windows and holds TVS path closed for 50ns upon transient detection, ensuring full energy absorption (30A peak) while preventing false triggering during sequencing ramps (<1mV/µs)
Expected Effect : Isolation >10kΩ (95% duty), response <1ns, leakage <50µA, 30A transient handling preserved
Risk Control :
  • GaN switch thermal management at 100MHz
  • clock jitter causing duty cycle variation ±5%
  • parasitic inductance in 10ns pulse path

Problem Direction 2 :

ImproveInter-rail isolation impedance
VS
ConstraintProtection energy absorption capacity

Inspiration 1 : Cross-domain reference

Application Principle: #19 Periodic action
Cross-domain applicability Assess applicability
Transition metal/zeolite SCR catalysts
Innovative Solution Refine solution

Time-division multiplexed TVS with nanosecond duty cycling for sequencing-aware protection

Rapid duty-cycle switching between isolation and protection modes
How to solve :
  • Implement 100MHz time-division multiplexing where TVS path alternates between high-isolation state (9.5ns, >50kΩ) and low-impedance state (0.5ns, <0.1Ω) using GaN FET switches with 0.3ns transition time
  • Deploy local energy buffer capacitors (47µF ceramic, X7R dielectric) at each rail to absorb transient energy during isolation phases, maintaining protection continuity with <2% voltage droop
  • Integrate dV/dt threshold detector (comparator with 1V/ns trip point) that extends low-impedance phase to 50ns when transient detected, capturing 30A peak current while time-averaged impedance remains >10kΩ during sequencing
Expected Effect : Time-averaged isolation >10kΩ, peak current handling 30A, leakage <50µA
Risk Control :
  • GaN FET gate drive timing jitter exceeding ±0.2ns
  • buffer capacitor ESR variation affecting transient response
  • dV/dt detector false triggering on high-frequency noise

Problem Direction 3 :

ImproveTVS conduction threshold voltage
VS
ConstraintTransient clamping response time

Inspiration 1 : Cross-domain reference

Application Principle: #28 Mechanics substitution
Cross-domain applicability Assess applicability
Method and apparatus for controlling power supply to a protected electrical load
Innovative Solution Refine solution

Voltage-controlled depletion-mode FET gate modulation for adaptive TVS threshold

Replace passive TVS with field-effect control
How to solve :
  • Replace conventional silicon TVS diodes with depletion-mode GaN HEMTs (e.g., EPC2001) whose threshold is electrically tunable via gate bias — 0V gate yields 0.8V threshold for normal protection, −5V gate raises threshold to 6V during sequencing, blocking 3-5V differentials while maintaining <3ns turn-on via capacitive gate coupling
  • Implement capacitive dV/dt sensor using 10pF high-speed capacitor and 50Ω resistor forming differentiator circuit — outputs gate bias proportional to voltage slew rate: sequencing ramps (<1mV/µs) generate <0.1V bias (device conducts normally), transients (>1V/ns) generate >5V bias triggering instant conduction within 2ns gate charging time
  • Integrate local Schottky pre-clamp (MBRS340, 0.4V forward drop) in series with 2Ω current-limiting resistor at each rail — absorbs initial 5A transient surge during the 2-3ns GaN HEMT activation delay, preventing voltage overshoot while GaN device assumes full 30A load, maintaining >12kΩ isolation during sequencing via reverse-biased Schottky junction
Expected Effect : Threshold voltage adaptive 0.8V→6V; response time <3ns; isolation >12kΩ during sequencing; 30A peak handling maintained
Risk Control :
  • GaN HEMT gate oxide breakdown under ESD stress
  • dV/dt sensor false triggering from high-frequency noise
  • Schottky pre-clamp thermal runaway at sustained current

Problem Direction 4 :

ImprovePower sequencing state isolation reliability
VS
ConstraintCircuit implementation complexity

Inspiration 1 : Cross-domain reference

Application Principle: #6 Universality
Cross-domain applicability Assess applicability
Chargeable device and charging method
Innovative Solution Refine solution

Dual-function TVS diode with integrated sequencing state sensing

Integrate TVS with leakage sensing function
How to solve :
  • Exploit TVS diode reverse leakage current as sequencing state indicator: <1µA during normal sequencing (>10kΩ isolation), >10µA when rail differential <0.3V (safe to enable protection)
  • Embed micro-current comparator (threshold 5µA) within TVS package using existing die area, output digital enable signal to gate series MOSFET with 8ns turn-on time
  • Connect back-to-back MOSFET pair (Rds(on)<0.05Ω) in series with each TVS diode, controlled by integrated comparator output—blocks cross-conduction during sequencing, enables <10ns transient response after rails converge
Expected Effect : Component count 6-9 (vs 15-25), board area +15% (vs +50%), isolation >50kΩ during sequencing, leakage <20µA, transient response <10ns, energy handling 25A peak
Risk Control :
  • Leakage current threshold drift over temperature (-40°C to +125°C)
  • comparator false triggering from high dI/dt noise
  • MOSFET gate charge delay extending response time beyond 10ns

Problem Direction 5 :

ImproveTransient clamping response time
VS
ConstraintMust not deteriorate

Inspiration 1 : Cross-domain reference

Application Principle: #10 Preliminary action
Cross-domain applicability Assess applicability
Power supply device for motor protector and power supplying method thereof
Innovative Solution Refine solution

Pre-biased gate TVS with sequencing-aware bias injection for adaptive response timing

Pre-bias TVS gates before sequencing to enable sub-5ns activation when transients occur
How to solve :
  • Install depletion-mode GaN FETs in series with each TVS diode, with gate pre-biased to threshold-minus-0.3V during normal operation for <5ns turn-on
  • inject reverse gate bias of +4V during sequencing windows (detected by power management IC enable signals) to block conduction and maintain >15kΩ isolation
  • transition bias states in <2ns using low-capacitance (5pF) gate drive circuits with 500mA peak current capability
Expected Effect : Response time <5ns in protection mode, >15kΩ isolation during sequencing, 30A peak current handling preserved
Risk Control :
  • gate bias timing synchronization failure
  • GaN FET threshold voltage drift over temperature
  • parasitic oscillation in fast gate transitions

Problem Direction 6 :

ImproveInter-rail isolation impedance
VS
ConstraintMust not deteriorate

Inspiration 1 : Cross-domain reference

Application Principle: #10 Preliminary action
Cross-domain applicability Assess applicability
Electric power conversion apparatus
Innovative Solution Refine solution

Pre-biased depletion-mode FET isolation switch with sequencing-aware gate control

Pre-bias gate before sequencing starts
How to solve :
  • Install depletion-mode N-channel JFETs (e.g., Vishay 2N5457) in series with each TVS inter-rail path, with gate pre-biased to −3V during power-off state via 100kΩ pull-down resistor, maintaining channel resistance >15kΩ and blocking cross-conduction during sequencing
  • Connect JFET gates to power management IC's power-good signals through RC delay network (10kΩ + 1nF, 10µs delay) that releases gate bias to 0V only after all rails reach ±5% target voltage, reducing channel resistance to <0.08Ω for full transient protection with <1ns TVS response
  • Implement per-rail autonomous gate control using voltage comparator (TLV7011, 500ns response) monitoring local rail voltage against 90% threshold, driving JFET gate through 50Ω series resistor to prevent gate oscillation, with 0.1µF local bypass capacitor ensuring stable bias during transients
  • Quality control: verify JFET off-state leakage <50µA at 5V differential (measure with picoammeter), on-state resistance <0.1Ω at 10mA (four-wire measurement), gate transition time <15µs (oscilloscope verification), and TVS clamping voltage within datasheet ±10% during 8kV IEC 61000-4-2 ESD test
Expected Effect : Isolation >15kΩ during sequencing, <0.1Ω when active; leakage <50µA; transient response <1ns maintained; component count +3 per rail
Risk Control :
  • JFET parameter variation across temperature −40°C to +125°C
  • gate bias timing mismatch causing brief conduction windows
  • JFET selection for adequate current rating
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