TVS Diode Failure Signature from Electrostatic Overstress

Overview of Technical Issues:

When electrostatic overstress events occur, the discharge source transmits excessive transient energy into the TVS diode's voltage-suppressing junction, creating a harmful thermal effect that exceeds the heat-dissipating substrate's cooling capacity; this insufficient heat removal causes localized overheating that degrades the semiconductor junction through melting or metallization damage, producing characteristic failure signatures (short or open circuit states) that compromise protection of the downstream circuit; the goal is to identify these failure signatures to improve EOS tolerance and maintain reliable circuit protection.

Solution directions generated for this problem

Problem Direction 1 :

ImproveTransient energy absorption capacity
VS
ConstraintDevice capacitance

Inspiration 1 : Cross-domain reference

Application Principle: #35 Parameter changes
Cross-domain applicability Assess applicability
Low-power-consumption semiconductor memory and driving method thereof
Innovative Solution Refine solution

Graded doping concentration profile TVS junction for enhanced EOS tolerance

Implement graded doping profile in TVS junction
How to solve :
  • Design graded doping concentration profile with high-density core (5×10¹⁸ cm⁻³) for energy absorption and low-density periphery (8×10¹⁷ cm⁻³) to minimize capacitance contribution, maintaining total capacitance 50–180 pF
  • Execute multi-step ion implantation using phosphorus at 80–150 keV for core region (central 60% area) and 40–60 keV for peripheral region, followed by rapid thermal annealing at 1050°C for 15 seconds to activate dopants and create smooth concentration gradient
  • Implement SIMS depth profiling quality control to verify doping concentration gradient within ±12% tolerance, junction depth uniformity ±0.08 μm, and capacitance measurement at 1 MHz confirming <200 pF across production batches
Expected Effect : Energy absorption +40–55%, capacitance increase <15%, EOS tolerance 2.2–2.8× baseline
Risk Control :
  • doping gradient uniformity deviation
  • annealing-induced dopant redistribution
  • peripheral region capacitance contribution higher than designed

Problem Direction 2 :

ImproveTransient energy absorption capacity
VS
ConstraintManufacturing cost

Inspiration 1 : Cross-domain reference

Application Principle: #35 Parameter changes
Cross-domain applicability Assess applicability
Terephthalic acid esters formation
Innovative Solution Refine solution

Dynamic ion implantation depth modulation for cost-effective EOS energy absorption

Modulate ion implant energy absorption via depth
How to solve :
  • Adjust ion implantation energy from standard 80keV to 150-180keV to create deeper junction profiles (depth 1.2-1.8µm vs standard 0.6-0.8µm), tripling energy absorption volume without increasing die area
  • Implement dual-energy implantation: shallow implant at 60keV (surface doping 5×10¹⁹ cm⁻³) for fast clamping, deep implant at 160keV (bulk doping 2×10¹⁸ cm⁻³) for energy spreading—uses existing implanters with modified recipes
  • Optimize rapid thermal annealing profile to 1050-1100°C for 15-25 seconds (vs standard 950°C/30s) to activate deeper dopants and create graded concentration gradient that distributes thermal stress across larger volume, preventing localized hotspots
Expected Effect : EOS energy handling +180-220%, manufacturing cost +8-12% (equipment reuse, no new materials)
Risk Control :
  • deeper junction increases leakage current risk
  • annealing uniformity across wafer batch
  • implant dose calibration drift over time

Problem Direction 3 :

ImproveHeat dissipation rate
VS
ConstraintManufacturing cost

Inspiration 1 : Cross-domain reference

Application Principle: #25 Self-service
Cross-domain applicability Assess applicability
Integrated energy generation damper
Innovative Solution Refine solution

Self-cooling metallization layer with integrated lateral heat spreading for TVS diodes

Repurpose existing metallization as heat spreader
How to solve :
  • Increase top aluminum metallization thickness from standard 3–5 µm to 12–18 µm using existing sputtering equipment with extended deposition time (no new tooling required)
  • Design radial spoke pattern in metal layer extending 1.5–2 mm beyond junction perimeter to conduct heat laterally away from hotspot, utilizing waste metal area already present in die layout
  • Add thermal anchor pads at spoke terminals connecting to package leadframe, creating direct conductive path from junction to external heat sink using only standard wire bonding process
Expected Effect : Lateral thermal conductivity +180%, heat dissipation rate +40–55%, zero substrate cost increase, processing time +8–12%
Risk Control :
  • metallization adhesion under thermal cycling stress
  • uniformity of thick metal deposition across wafer
  • electrical parasitic effects from enlarged metal geometry

Problem Direction 4 :

ImproveTransient energy absorption capacity
VS
ConstraintMust not deteriorate

Inspiration 1 : Cross-domain reference

Application Principle: #1 Segmentation
Cross-domain applicability Assess applicability
Transmit QoS requirements and UE power preferences in LTE-A networks
Innovative Solution Refine solution

Spatially-segmented dual-zone TVS junction architecture for independent energy-capacitance optimization

Divide junction into isolated functional zones
How to solve :
  • Partition the TVS die into a central deep energy-absorption core (占15–20% footprint, junction depth 8–12 μm, doping 1×10^17 cm⁻³) surrounded by shallow peripheral guard rings (depth 2–3 μm, doping 5×10^16 cm⁻³)
  • core handles EOS transients via large depletion volume, periphery clamps voltage with minimal capacitance contribution
  • Implement selective ion implantation masking: first implant shallow periphery at 80 keV, then mask periphery and implant core at 180 keV with 900°C rapid thermal anneal for 30s to form distinct depth profiles without lateral diffusion beyond ±0.3 μm
  • Connect zones via segmented metallization with 50 μm isolation trenches filled with benzocyclobutene (BCB) dielectric (εᵣ=2.65) to electrically parallel zones while spatially isolating capacitance fields—total device capacitance remains 60–85 pF while core absorbs 3–5× energy of conventional single-zone design
Expected Effect : Energy absorption +280%, capacitance held <85pF, EOS tolerance to 15kV HBM
Risk Control :
  • Implant mask alignment precision <0.5μm required
  • BCB trench void formation risk
  • thermal mismatch stress between zones
Patsnap Eureka Solution