TVS Diode Reverse Recovery Time Impact on Switching Circuits

Overview of Technical Issues:

During switching transitions, the TVS diode's finite reverse recovery time creates a harmful effect where reverse recovery current flows through the switching element, causing excessive switching losses, voltage overshoots, and potential electromagnetic interference; the goal is to minimize this harmful interaction while maintaining effective transient voltage protection in high-frequency switching circuits.

Solution directions generated for this problem

Problem Direction 1 :

ImproveReverse recovery speed
VS
ConstraintTransient voltage clamping capability

Inspiration 1 : Cross-domain reference

Application Principle: #1 Segmentation
Cross-domain applicability Assess applicability
A fast recovery diode structure and its manufacturing method
Innovative Solution Refine solution

Depth-Segmented Dual-Junction TVS with Functional Layer Separation

Vertically segment TVS into shallow fast-recovery and deep clamping layers
How to solve :
  • Fabricate shallow N-type junction (0.3-0.5μm depth) with low doping (1×10¹⁵ cm⁻³) atop deep P-type region (8-12μm, 5×10¹⁷ cm⁻³) using sequential ion implantation and annealing at 950°C for 30min
  • Shallow junction handles switching transitions with <10ns recovery time and <0.3A peak current due to minimal stored charge
  • Deep junction activates only during surge events (>20V threshold) via avalanche breakdown, injecting high carrier density to achieve 15V clamping at 600W peak power
Expected Effect : Recovery time <10ns; clamping voltage 15V±0.5V at 600W; switching loss <5%
Risk Control :
  • Junction depth control tolerance ±0.05μm
  • doping concentration uniformity <3% variation
  • thermal budget management during dual implantation

Problem Direction 2 :

ImproveReverse recovery speed
VS
ConstraintEnergy absorption capacity

Inspiration 1 : Cross-domain reference

Application Principle: #1 Segmentation
Cross-domain applicability Assess applicability
Fabrication methods of silicon-based diodes, silicon-based diodes, and diode devices.
Innovative Solution Refine solution

Spatially-segmented dual-junction TVS architecture for independent recovery and energy handling

Spatially segment TVS into parallel fast-recovery and high-energy paths
How to solve :
  • Fabricate dual-junction TVS structure with shallow trench (0.3-0.5μm depth) fast-recovery junction achieving <10ns recovery, and deep mesa (8-12μm) high-energy junction providing 600W capacity
  • Implement differential doping profile—shallow junction uses low-lifetime gold doping (τ<5ns) with charge storage <50pC, deep junction uses standard lifetime (τ=100-200ns) with charge storage >500pC for surge absorption
  • Connect junctions in parallel with isolation trench (1-2μm width, oxide-filled) preventing charge sharing—fast junction activates during switching transitions (<100V/μs slew rate), energy junction activates during surges (>1kV/μs slew rate) via voltage-dependent turn-on
Expected Effect : Recovery time <10ns, energy capacity 600W, recovery current <0.5A, switching loss <5%
Risk Control :
  • trench depth uniformity ±0.05μm tolerance
  • doping concentration mismatch between junctions
  • isolation trench leakage under high voltage

Problem Direction 3 :

ImproveReverse recovery current magnitude
VS
ConstraintTransient voltage clamping capability

Inspiration 1 : Cross-domain reference

Application Principle: #10 Preliminary action
Cross-domain applicability Assess applicability
Encapsulation liquid lubricant for tablet compression
Innovative Solution Refine solution

Pre-discharge pulse circuit for TVS charge extraction before switching transitions

Extract stored charge before switching occurs
How to solve :
  • Integrate a synchronized pre-discharge circuit that injects a controlled extraction pulse 50-100ns before each MOSFET turn-on event, removing 80-90% of stored charge from the TVS junction
  • Use a fast gate-drive timing controller (resolution ≤10ns) to trigger a 20-50mA extraction current through a parallel discharge path with 10Ω series resistor, reducing peak recovery current to <0.5A
  • Maintain full TVS charge storage between switching cycles—the extraction pulse duration (30-50ns) is 100× shorter than the switching period (10μs at 100kHz), allowing complete charge restoration for 15V clamping during actual transient events
Expected Effect : Recovery current <0.5A; clamping voltage maintained at 15V; switching loss <5%
Risk Control :
  • timing synchronization jitter exceeding ±15ns
  • extraction pulse amplitude variation >10%
  • parasitic inductance limiting discharge speed

Problem Direction 4 :

ImproveReverse recovery current magnitude
VS
ConstraintEnergy absorption capacity

Inspiration 1 : Cross-domain reference

Application Principle: #1 Segmentation
Cross-domain applicability Assess applicability
Solid-state imaging device and method of operating the same, and electronic apparatus and method of operating the same
Innovative Solution Refine solution

Spatially-segmented dual-TVS architecture with functional zone separation

Dual-TVS architecture with functional separation
How to solve :
  • Deploy fast-recovery TVS (Schottky-barrier or SiC-based, trr<10ns, Qrr<50nC) directly at switching node within 5mm trace length to intercept recovery current, limiting peak to <0.5A during 100kHz transitions
  • Position high-energy TVS (standard PN junction, 600W peak, 1kW·μs energy rating) on DC bus 50-100mm away with series inductance 100-220nH to decouple high-frequency switching from surge events
  • Implement impedance-based frequency discrimination — fast TVS presents low impedance (<0.5Ω) at >10kHz switching frequencies, while series inductor blocks high di/dt (limiting to 50A/μs), but saturates or becomes transparent during slow-rising (>1μs) ESD/lightning transients, directing full surge energy to high-capacity TVS
Expected Effect : Recovery current <0.5A, switching loss <5%, energy absorption maintained at 600W, EMI reduction 12dB
Risk Control :
  • trace inductance coupling between TVS zones
  • inductor saturation threshold calibration
  • thermal management for dual-device layout

Problem Direction 5 :

ImproveSwitching loss level
VS
ConstraintTransient voltage clamping capability

Inspiration 1 : Cross-domain reference

Application Principle: #2 Taking out
Cross-domain applicability Assess applicability
Insulating trenches for ESD circuits
Innovative Solution Refine solution

Dual-path TVS architecture with fast-recovery primary and high-energy secondary protection

Separate protection into two independent paths
How to solve :
  • Install a low-capacitance Schottky barrier TVS (10pF, <5ns recovery) directly at the switching node for high-frequency operation, physically isolated from a high-energy avalanche TVS (600W, 15V clamping) positioned 20-50mm away on the DC bus via dedicated PCB trace routing
  • Configure the fast-recovery path with series gate resistor (2-5Ω) to limit di/dt to <100A/μs during switching transitions, reducing MOSFET turn-on losses to <5% while maintaining <0.3A peak recovery current
  • Design the high-energy path with thick junction structure (>50μm depletion width) and connect through low-inductance bus bar (<10nH) to handle ESD surges up to 8kV contact discharge and lightning-induced transients, triggered only when voltage exceeds 18V threshold
Expected Effect : Switching loss <5%, clamping voltage 15V±0.5V, energy absorption 600W peak, recovery time <5ns
Risk Control :
  • PCB trace inductance coupling between paths
  • thermal management for high-energy TVS under repetitive surges
  • tolerance matching between dual TVS breakdown voltages

Problem Direction 6 :

ImproveSwitching loss level
VS
ConstraintEnergy absorption capacity

Inspiration 1 : Cross-domain reference

Application Principle: #1 Segmentation
Cross-domain applicability Assess applicability
Drive circuit for voltage driven electronic element
Innovative Solution Refine solution

Dual-path TVS architecture with fast-recovery front stage and high-energy backend stage

Divide protection into two physically separated TVS devices optimized independently
How to solve :
  • Install a low-capacitance fast-recovery TVS (trr<10ns, Qrr<50nC) directly at the switching node within 5mm trace length to intercept reverse recovery current during transitions, limiting peak Irr to <0.5A and reducing MOSFET turn-on losses to <5%
  • Position a high-energy TVS (600W peak, 10/1000μs pulse rating) on the DC bus 50-100mm away with series inductance 100-200nH acting as decoupling element—this backend stage handles ESD and lightning surges without affecting switching dynamics
  • Use Schottky barrier TVS (VBR=18V±5%, Cj<100pF) for front stage and avalanche junction TVS (VBR=15V±10%, junction area 2mm²) for backend stage, with coordinated breakdown voltages ensuring front stage clamps fast transients while backend absorbs high-energy events exceeding 10μJ
Expected Effect : Switching loss <5% vs baseline 20%; Energy absorption maintained at 600W; Recovery current <0.5A; Front TVS trr=8ns, backend energy rating 600W verified per IEC 61000-4-5
Risk Control :
  • Front TVS thermal runaway under repetitive switching
  • Parasitic inductance between stages causing voltage overshoot
  • Backend TVS coordination failure during mixed transient events

Problem Direction 7 :

ImproveEMI emission level
VS
ConstraintTransient voltage clamping capability

Inspiration 1 : Cross-domain reference

Application Principle: #22 Blessing in disguise
Cross-domain applicability Assess applicability
Clothing processing equipment
Innovative Solution Refine solution

Ferrite-core TVS with EMI energy harvesting for enhanced clamping

Convert EMI energy into clamping boost
How to solve :
  • Integrate a nanocrystalline ferrite toroid (permeability μ=15,000-20,000) directly into the TVS package, positioned 0.6mm from the junction — captures di/dt energy during reverse recovery as magnetic flux
  • During normal switching, the ferrite core absorbs high di/dt transients (limiting dI/dt to <50A/μs), suppressing conducted EMI by 12-15dB in 10-100MHz range to achieve Class B compliance
  • When surge events occur (>50V threshold), stored magnetic energy releases within 20ns via flux-assisted avalanche triggering, injecting additional charge carriers into the depletion region to reduce clamping voltage from baseline 22V to target 15V while maintaining 600W energy absorption
Expected Effect : EMI suppression 12-15dB; clamping voltage 15V maintained; energy capacity ≥600W; switching loss <8%
Risk Control :
  • ferrite saturation under repetitive surges
  • thermal coupling between core and junction
  • flux-assisted triggering timing precision

Problem Direction 8 :

ImproveEMI emission level
VS
ConstraintEnergy absorption capacity

Inspiration 1 : Cross-domain reference

Application Principle: #24 Intermediary
Cross-domain applicability Assess applicability
Super-junction MOSFET device and preparation method thereof
Innovative Solution Refine solution

Ferrite-core TVS with magnetic energy buffering for EMI suppression and surge absorption

TVS with integrated magnetic buffer decouples EMI and energy functions
How to solve :
  • Integrate a ferrite core sleeve (material: MnZn ferrite, μr=2000-3000) around the TVS cathode lead as a magnetic intermediary — limits di/dt to <50A/μs during reverse recovery, suppressing EMI by 12-15dB to Class B compliance in 10-100MHz range, while the TVS junction retains standard charge storage for 600W energy absorption
  • Core saturates at threshold current 3A within 20ns during high-energy transients (ESD/lightning), becoming magnetically transparent and allowing full 600W peak power dissipation through the TVS junction without impedance
  • Specify ferrite geometry: 0.8mm wall thickness, 3mm length, saturation flux density Bsat ≥0.4T — fabricated via co-sintering with TVS package or press-fit assembly, ensuring <0.3mm air gap tolerance for consistent saturation behavior
Expected Effect : EMI reduced 12-15dB; 600W energy capacity retained; recovery current <0.5A
Risk Control :
  • ferrite Bsat variation ±10% affecting saturation threshold
  • thermal cycling causing core-lead delamination
  • parasitic capacitance from ferrite increasing at >50MHz
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