TVS Diode Voltage Clamp Stability Under Repetitive ESD

Overview of Technical Issues:

## Part 2: Natural Language Summary Under repetitive ESD events, the TVS diode's voltage-clamping semiconductor structure exhibits insufficient voltage constraining function due to thermal accumulation exceeding heat dissipation capacity, causing clamping voltage drift and instability that allows transient overvoltage to reach the protected circuit; the goal is to maintain stable clamping voltage characteristics throughout repetitive ESD stress conditions.

Solution directions generated for this problem

Problem Direction 1 :

ImproveHeat dissipation capacity
VS
ConstraintDevice structural complexity

Inspiration 1 : Cross-domain reference

Application Principle: #1 Segmentation
Cross-domain applicability Assess applicability
Lighting and display devices
Innovative Solution Refine solution

Localized thermal via clustering in high-current junction zones

Divide thermal pathway into independent zones targeting high-current regions only
How to solve :
  • Identify high-current density zones (>500 A/cm²) in TVS junction via thermal simulation and place clustered thermal via arrays (via diameter 50–80μm, pitch 100–150μm) exclusively in these 15–25% footprint regions instead of full-area metallization
  • Implement 3-zone segmented thermal architecture: Zone-A (junction center, 4×4 via cluster), Zone-B (intermediate ring, 2×2 cluster), Zone-C (periphery, passive conduction), each zone thermally independent with localized metal routing on existing 8-layer stack
  • Increase top metal thickness from 2μm to 6μm only above via clusters using selective electroplating (plating time 45–60 min, current density 2–3 A/dm²), maintaining 2μm elsewhere to avoid adding fabrication layers
Expected Effect : Junction-to-substrate thermal resistance <0.5°C/W; fabrication layers 10–11 vs baseline 14+; clamping voltage drift reduced to ±4% under >1kHz ESD
Risk Control :
  • via placement accuracy ±5μm required
  • electroplating thickness uniformity within ±0.4μm
  • thermal zone boundary thermal crosstalk

Problem Direction 2 :

ImproveHeat dissipation capacity
VS
ConstraintManufacturing precision requirement

Inspiration 1 : Cross-domain reference

Application Principle: #11 Beforehand cushioning
Cross-domain applicability Assess applicability
LED with ceramic green phosphor and protected red phosphor layer
Innovative Solution Refine solution

Redundant thermal via array with design margin for relaxed epitaxial tolerance

Redundant thermal via design relaxes precision
How to solve :
  • Design thermal via array with 20% redundancy beyond minimum thermal requirement — extra vias compensate for epitaxial thickness variation
  • Relax epitaxial layer thickness tolerance from ±0.3μm to ±0.6μm while maintaining junction-to-substrate thermal resistance <0.5°C/W through via count buffer
  • Implement statistical process control — measure via density ≥150 vias/mm² and verify thermal resistance by infrared thermography at 1kHz ESD pulse trains
Expected Effect : Epitaxial tolerance relaxed to ±0.6μm; doping profile tolerance ±8%; thermal resistance maintained <0.5°C/W; clamping voltage drift reduced to ±4%
Risk Control :
  • via fabrication yield variation
  • thermal resistance measurement accuracy
  • redundant via cost increase

Problem Direction 3 :

ImproveClamping voltage stability
VS
ConstraintDevice structural complexity

Inspiration 1 : Cross-domain reference

Application Principle: #35 Parameter changes
Cross-domain applicability Assess applicability
Charge pump stability control
Innovative Solution Refine solution

Wide-bandgap semiconductor material substitution for temperature-insensitive voltage clamping

Replace silicon with wide-bandgap material for intrinsic thermal stability
How to solve :
  • Substitute silicon junction with 4H-SiC epitaxial layer (bandgap 3.26eV vs Si 1.12eV) — temperature coefficient reduced from −2.2mV/°C to −0.4mV/°C, maintaining 15V ±2% across 15–25°C junction temperature rise without additional thermal layers
  • Fabricate using 8-layer standard process: substrate preparation, 4–6μm epitaxial growth at 1550–1600°C, ion implantation doping (nitrogen 1×10¹⁷ cm⁻³), nickel silicide contact formation, single-layer aluminum metallization (2μm), passivation — no multi-layer thermal vias or heat spreaders required
  • Implement edge termination with single guard ring (width 8–12μm, depth 0.8μm) to maintain breakdown voltage uniformity ±4%, ensuring clamping voltage drift ≤±3% (14.55–15.45V) under repetitive ESD stress at >1kHz without structural complexity increase
Expected Effect : Clamping voltage stability ±2% vs ±8% baseline; 8-layer vs 14+ layer fabrication; thermal resistance <0.6°C/W
Risk Control :
  • SiC wafer cost 8–12× silicon baseline
  • epitaxial thickness control ±0.4μm criticality
  • contact resistance variability 15–25%

Problem Direction 4 :

ImproveThermal energy transfer rate
VS
ConstraintMust not deteriorate

Inspiration 1 : Cross-domain reference

Application Principle: #19 Periodic action
Cross-domain applicability Assess applicability
Radio communication device and radio communication method
Innovative Solution Refine solution

Pulsed thermal extraction with inter-pulse thermal buffering via time-phased heat sink activation

Time-phased heat sink with pulse-triggered activation
How to solve :
  • Integrate a dual-layer thermal pathway: inner high-conductivity copper layer (0.6mm thick, ≥380 W/(m·K)) bonded to TVS junction for fast extraction, outer phase-change material buffer (paraffin wax PCM, melting point 58-62°C, latent heat ≥200 kJ/kg, 1.2mm thick) activated only during pulse trains
  • Embed micro-thermoelectric sensors (response time <1μs) at junction interface to detect ESD onset
  • trigger signal activates piezoelectric actuator that compresses PCM layer by 15–25% within 8μs, reducing thermal resistance from 1.2°C/W to 0.35°C/W during pulse extraction phase
  • Between pulses (10-50μs gaps), actuator releases compression allowing PCM to expand and re-solidify, restoring thermal buffering capacity to prevent junction thermal cycling
  • cycle repeats per detected pulse with <5μs switching latency
Expected Effect : Junction temp rise reduced to 6-9°C per pulse train; clamping voltage drift ≤4% (14.4-15.6V); thermal time constant 12μs during extraction, 65μs buffering between pulses; handles >1kHz repetitive ESD
Risk Control :
  • PCM phase transition consistency over 10⁶ cycles
  • piezoelectric actuator fatigue and response delay
  • sensor-actuator synchronization timing jitter ±2μs
Patsnap Eureka Solution