Memory Adressing/Allocation/Relocation TRIZ Cases
- OS Scheduler Adjusts CPU Time Quantum for Fair Cache Sharing
Operating system scheduler computes fair CPU latency based on cache miss rates and CPI values to resolve co-runner dependency performance variability.
- Time Annotated Transaction Level Modeling for Cycle Timing Accuracy
Time annotated transaction level modeling uses timing variable functions to store and derive precise cycle timing information within burst transactions.
- IOMMU Self-Invalidated Page Table Entries
IOMMU page table entries use removal rules for autonomous self-deletion, eliminating CPU overhead in virtualized I/O transactions.
- Dynamic Memory Management for Workload Acceleration
A memory condition module determines host and device parameters to select optimal memory management methods.