Memory Adressing/Allocation/Relocation TRIZ Cases
- Neural Network Systolic Array for Low-Latency On-Chip Rearrangement
Internal memory banks and rearrangement interfaces move tensors on-chip, reducing layer-transition latency in systolic neural accelerators.
- Register Renaming Cache to Reduce RAT Complexity and Power
This processor case caches renaming data from instruction traces to reduce RAT complexity, power use, and critical timing pressure.