Neural Architectures TRIZ Cases
- ASIC Tile Architecture for Parallel Neural Network Computation
Tile-based ASIC arrays with local memory and controllable bus lines cut neural network latency and improve bandwidth through parallel processing.
- Analog Multiplier Array Sparsity for Low-Power Neuromorphic Circuits
Ground-wired two-quadrant multipliers and zero-driven weights cut neuromorphic chip power while preserving machine learning throughput.
- Lookup-Table Neural Network Circuit for Low-Power Inference
Precomputed lookup tables replace neural-network multipliers to cut power and chip area while preserving practical inference speed.
- Nonlinear RF Pre-Distortion Using Machine Learning Feedback
Neural-network pre-distortion compensates amplifier nonlinearity, enabling high RF output power with lower distortion and interference.
- Post-Synaptic Inverting Circuits for Smooth Neuromorphic Transfer Curves
Series-connected inverting circuits shape a smoother sigmoid-like neuron output, enabling multi-level synaptic signal representation.
- ASIC Tile Architecture for Parallel Neural Network Acceleration
Parallel ASIC tiles combine computational arrays, local memory, and controllable bus lines to cut neural network latency and raise bandwidth.
- Neural Network Predistortion for High-Power Radio Linearity
A neural network predistorts transmit radio signals so amplifiers can run near maximum power while limiting distortion and interference.