Neural Architectures TRIZ Cases

Composition conversion apparatus adjusts neural network layer parameters to increase computation amount.

Frequency modulation of pre-synaptic spikes within a synaptic unit overcomes the limited dynamic range of analog current conversion in hardware neural networks.

A grouping unit clusters event generation elements to output group addresses via generated signals.

Iterative pruning guided by sensitivity analysis reduces computational needs while maintaining prediction accuracy.

A deep neural network model fuses parameters from multiple source models into a single unified structure to generate combined output data.

Distributing synaptic weights across multiple signed analog conductance pairs of varying significance to enhance dynamic range.

Voxel-based light transport simulation resolves the contradiction between rendering accuracy and image fidelity for translucent materials.

Segmenting convolution tasks across parallel computing units reduces data transport volume and power consumption for edge device inference.

An FSF architecture dynamically selects features to forecast IoT traffic.

Timestep splitting and membrane potential measurement accelerate spiking neural network training by identifying non-contributing images.

Arrays of 3x3 convolutional filter kernels approximate fully-connected layers, eliminating external CPU or GPU processing bottlenecks.

A reconfigurable neuron device uses ion gate regulation to control magnetic domain wall motion for spike signal output.

A reservoir computing apparatus uses a memristor array to perform dimension raising and nonlinear operations.

A neuron bus serially transmits postsynaptic firing indications between neuromorphic cores using transmit and receive buffers.

Segmenting processing units allows shared controllers and data buses, reducing external memory access and power consumption.

Segmented GANs encode subjective traits into latent vectors, enabling precise manipulation of social impressions without compromising photorealism.

Arithmetic processing device scales weights and biases by positive constants to enable consistent fixed-point bit lengths across convolutional layers.

The Inconsistent Stochastic Gradient Descent algorithm dynamically adjusts training iterations based on batch loss to accelerate convergence.

Learnable quantization threshold parameters eliminate input data distribution restrictions and reduce calculation costs in fixed-point neural networks.

Machine learning classifies application modules via metadata analysis to resolve deployment accuracy and efficiency trade-offs.

Segmenting networks into projection layers reduces computational resource consumption while maintaining processing capability.

Integrating synaptic coefficient memories and buffer units on a single chip reduces electrical consumption by eliminating inter-chip data exchanges.

A neural network generates plant-based food formulas by sampling from a latent space of ingredient embeddings.

A neural architecture search system evaluates candidate networks using weight-related ranking metrics to determine performance.

A hybrid neural network model integrates different neuron types within intermediate layers to balance accuracy and efficiency.

A three-level neural network model extracts feature information and interaction representations through segmented processing stages.

Binary sample matrices replace weight matrices during inference to resolve the contradiction between reduced computational cost and deteriorated accuracy.

A neural network apparatus updates autoencoder parameters using calculated contribution values to preserve existing learning information during retraining.

A biologically plausible neural network framework uses dendritic segments and excitatory-inhibitory populations to process context-dependent information.

Invertible wavelet layers replace pooling operations to eliminate information loss and computational waste in image restoration.

Attention map distillation bridges architecture gaps to preserve temporal information during knowledge transfer.

A gradient accumulator generates free momentum between training passes using a single memory element.

Grouping input channels with dedicated kernels reduces computation while maintaining inference accuracy.

Differential weight updates reduce data transmission latency and device energy consumption while maintaining computational accuracy in IoT environments.

Dynamic activation thresholds adapt to input overlap values, resolving fixed-parameter bottlenecks and improving generalization without extra memory.

Adapting encoding configurations for temporally encoded data sequences mitigates decoding errors caused by communication delays and jitters.

A neural network selects model neurons via sparse decoding vectors to reduce computational units.

Stacked deep learning detects malicious traffic in IoT networks using residual networks, isolating compromised devices to mitigate cyber threats.

An acoustic model learning device generates synthetic voices with natural intonation using speaker and voice determination models.

A meta-learning apparatus generates task vectors to predict response variables across diverse tasks using minimal training data.

A learning apparatus divides target data into partial pieces processed by multiple network models to generate prediction results and confidence values.

A neural network device selects variable class combinations to identify specific data types.

Analyzing feature space separability during training adjusts parameters to resolve poor class separation and reduce false positives.

A pseudolabel generator computes maximum a posteriori probability estimates to substitute noisy labels during machine learning model training epochs.

A dual artificial neural network architecture generates utterance match and mismatch synthesis images to enhance lip sync realism.

A swipe input processing system normalizes trajectory data to extract shape and relative position features for character determination.

A resistive memory artificial neuron integrates excitatory and inhibitory inputs via variable resistance states to produce threshold-based output signals.

Rank-based scaling factors adjust node activation values during neural network training to improve computational efficiency.