Physical Realisation TRIZ Cases
- Sparse Jacobian Forward Training for Recurrent Neural Networks
Forward propagation with sparse Jacobian masks cuts RNN training memory and computation for long sequences while preserving accuracy.
- Streaming Convolution Buffering for Low-Memory Neural Processors
Partial tensor buffering lets neural processors stream multi-layer convolutions with lower memory footprint, latency, and power use.
- Neural Network Training Memory Profiling for Low-Latency Updates
Model profiling selects training techniques such as activation recomputation and remote loading to cut memory use and iteration latency.
- Softmax Fractional Exponential Computation on Matrix Accelerators
Matrix multiplication hardware computes softmax fractional exponentials through binary scaling and polynomial conversion to cut computation time and raise throughput.
- Neural Network Code Generation With Memory Planning Proposals
Multiple memory plan proposals are evaluated before code generation to cut RAM use and installation time for neural networks on constrained devices.
- Edge NPU Scheduling for Parallel Multi-ANN Execution
A scheduler-driven edge NPU allocates processing elements across ANN models to cut idle time, delay, and power use.
- Flexible Bit Truncation in ML Layers for Speed-Precision Balance
Dynamic bit truncation in SRAM-backed ML layers cuts processing complexity and power use while preserving application-level accuracy.
- Neural Network Pruning Markers for Low-Power Edge Inference
Pruning markers track removable neural network weights, cutting edge inference compute and power while keeping loss within threshold.
- Distributed Model Parameter Aggregation for Faster Node Training
Combining parameters from separate memories before node transfer cuts DDR bandwidth use, reduces packet overhead, and speeds model training.
- Generative AI Information Gating for Traceable Model Outputs
Information gates filter prompt-linked input sets and monitor signals to improve generative AI traceability, accountability, and explainability.
- Neural Network Activator Circuit With Segmented SiLU Approximation
Piecewise linear SiLU activation with segmentation and error correction cuts DNN hardware latency and power for edge AI inference.
- Modular NPU AI Computing for Scalable Low-Power Inference
Standardized NPU modules replace fixed GPU architectures to scale AI compute while cutting power use, cost, and underutilized capacity.
- Ferroelectric FET Barrier Layer for Stable Memory Window
A diffusion barrier blocks oxygen exchange in a ferroelectric FET, preserving the channel while improving polarization switching and memory window.
- Deep Learning Computation Graph Fusion for Lower Cache Pressure
By fusing memory-intensive operators into compute-heavy ones and splitting sub-graphs, this case cuts cache pressure and optimization time.
- Photonic Computing Output Calibration for Signal Accuracy
Maps theoretical results to actual optical outputs so photonic computing can correct manufacturing deviations and interpret signals accurately.