Physical Realisation TRIZ Cases
- Context-Aware Memory Tiering for Deterministic ML Training
Deterministic training patterns guide tensor eviction and prefetching, freeing memory before backward computation.
- Reduced-Precision Neural Federated Learning for Lower Bandwidth
Quantized model weights reduce federated-learning bandwidth, processing power, and battery use while preserving privacy and acceptable accuracy.
- Physical Reservoir Element With Nonlinear Sample-and-Hold Circuit
Electronic physical reservoirs can lack short-term memory; integrated sample-and-hold and nonlinear circuits retain past signals for time-series processing.
- Teacher-Student Neural Network Distillation for Microcontrollers
A large CNN teacher trains a smaller student through staged composite losses, preserving model performance for microcontroller deployment.
- State Space Neural Network Codecs for Low-Power Data Compression
State space neural network codecs reduce parameter count and computational overhead for compressed time-series data on low-power devices.
- Graph-Based Neural Network Quantization-Aware Retraining for Edge NPUs
Markers capture graph-module values for scale and offset calibration, enabling integer retraining that lowers memory use and power on edge NPUs.
- Neural Network Blocks Using Grouped Convolution for Mobile Inference
Grouped convolution replaces depth-wise convolution to improve mobile classification accuracy while preserving computational efficiency and reducing latency.
- Distributed Deep Learning With Multi-NIC Allreduce Communication
Multiple NICs assign parallel communication paths to accelerators, easing Allreduce congestion and reducing distributed learning overhead.
- Federated Learning With Ordered Dropout for Heterogeneous Devices
Ordered dropout prunes neural network layers to match client capabilities, reducing stragglers while including low-tier devices in training.
- HBM CNN Architecture With Virtual Banks And On-Chip Buffer
Virtual HBM banks and an on-chip buffer limit feature-map movement between convolutional and depthwise units, reducing latency.
- Sparse Neural Network Hardware Architecture for Inactive-Value Skipping
Inactive-value skipping and partition alignment let sparse neural hardware reduce tensor operations, CPU bandwidth, and power use.