Processor Architectures/Configuration TRIZ Cases
- Kernel-Mediated GPU Allocation for Containerized Processes
Kernel interception maps process calls to containers and enforces GPU limits on graphics buffers to reduce waste and improve allocation fairness.
- Bounding Volume Hierarchy Reinsertions for Faster Ray Intersection Search
Selective BVH reinsertions resolve candidate conflicts and improve ray-intersection search efficiency without exhaustive tree updates.
- Hybrid Feedback Processing for Low-Latency User Input
A hybrid path combines dedicated low-latency hardware with software processing to provide immediate visual and tactile user feedback.
- Tile-Based Graphics Processing With Hierarchical Bounding Boxes
A multi-level bounding-box hierarchy groups primitives into packets, reducing tile tests and unnecessary memory access during rendering.
- Tile-Based Graphics Processing With Bounding Box Hierarchies
A two-pass bounding box hierarchy sorts primitives by position so each rendering tile processes relevant geometry with fewer unnecessary tests.
- GPU Register Allocation for Variable-Rate Fragment Shading
Variable fragment shading rates can over-allocate GPU registers; compiler-guided sizing matches resources to fragments and samples for better processing.
- Processor Settings API for Job-Aware Resource Scheduling
An API maps job characteristics to processor settings, balancing scheduling efficiency, clock frequency, core allocation, and resource use.
- Variable Fragment Shading Rates for Efficient Scene Rendering
Combining primitive and attachment shading rates lets tile-based renderers vary work by region and reduce unnecessary shading tasks.
- CPU Vertex Culling for Lower GPU Graphics Rendering Load
CPU-side culling removes vertex data outside the user’s field of view before GPU rendering, reducing GPU load during heavy graphics workloads.
- Graphics Processor Task Overlap for Rendering Dependencies
Overlapping rendering tasks across jobs uses shader-core status records to enforce dependencies, improve utilization, and shorten completion times.
- SOC Rendering Architecture for Multi-GPU Coordination
Multiple GPUs and operating systems use shared memory and inter-core communication to coordinate rendering tasks and improve resource use.
- Neural Processing Unit Sub-Kernel Convolution for Lower Latency
Dividing transpose-convolution kernels into sub-kernels avoids zero-value MACs, reducing latency in neural processing units.
- Shader Prologue Shared Functions for Constant Computation
Multiple shader instances reuse one prologue function to compute constants, reducing repeated work, constant-buffer access, and CPU bottlenecks.
- Systolic Array NPU Sub-Kernel Processing for Transpose Convolution
Dividing transpose-convolution kernels into sub-kernels lets systolic-array PEs skip zero-padded regions, reducing MACs and latency.
- Tile-Based Graphics Processing With Selective Redundancy
Selective tile duplication and output comparison protect critical graphics regions without duplicating the entire graphics pipeline.
- Auxiliary Engine Virtualization for Shared Image Frontend Processing
An auxiliary engine virtualizes frontend modules across image sensors, reducing redundant hardware, area penalties, and design cost.
- Heuristic Tiled Rendering Selection for Graphics Primitives
GPU heuristics select tiled rendering for large primitives and standard rendering for small ones, reducing memory bandwidth usage and improving performance.
- GPU State Programming Overhead Reduction Through Path Routing
When low-workload state commands move to a payload path, graphics processors reduce scheduling overhead and improve resource utilization.
- GPU Image Rendering and Encoding Without CPU-GPU Data Replication
Direct rendering, format conversion, and coding in GPU memory avoid CPU-GPU data copies, reducing processor use and latency.
- Graphics Rendering With Multi-Purpose Shader Handoff
A multi-purpose shader keeps scenes rendering while a task-specific shader loads, reducing runtime stuttering and GPU disruption.
- Tile-Based Graphics Processing with Deferred Geometry for Lower Bandwidth
Deferred geometry processing after preliminary binning reduces intermediate-data storage and memory bandwidth in tile-based graphics pipelines.
- GPU Graphics Rendering With Multi-Purpose Shader Fallbacks
A multi-purpose GPU shader keeps rendering active while task-specific shaders load, reducing runtime stuttering in gameplay.
- Texture-Space LOD Using Numerically Stable Eigenvalue Calculations
Numerically stable ellipse-axis calculations select texture-space mipmap levels with fewer operations, improving LOD accuracy while reducing chip area and power.