100G-KR Encoding With Burst Interleaving for Low Bit Error Rate
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Solution Overview
Problem
High-speed Ethernet networks, such as 100G-KR, face challenges in achieving low bit error rates and robustness against burst errors, which existing forward error correction schemes often compromise on latency, coding gain, and hardware complexity.
Innovation Solution
Implementing burst interleaving schemes and transcoding methods like 512B/514B and 256B/258B transcoding, combined with error correction codes like Reed-Solomon codes, to enhance error correction capabilities across multiple physical lanes, thereby improving robustness and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If forward error correction schemes are implemented to achieve low bit error rates, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error correction process into multiple independent stages: burst error detection, burst error correction, and remaining error correction. Each stage handles specific types of errors with dedicated algorithms, avoiding the need for a single complex error correction system. This segmentation allows each component to be optimized independently, reducing overall hardware complexity while maintaining high reliability.
Solution Approach 2:
The patent introduces an intermediary burst error correction stage that processes data between the physical layer and higher layers. This intermediary layer handles the most challenging burst errors first, simplifying the requirements for subsequent error correction stages and reducing the complexity of the overall system while improving bit error rate performance.
2Reliability
If forward error correction schemes are implemented to improve reliability, then burst error correcting capacity is improved, but loss of time increases
Solution Approach 1:
The error correction process is divided into sequential stages with increasing complexity: first a lightweight burst error correction stage that quickly handles the majority of errors, followed by additional correction stages only when needed. This segmentation ensures that most data packets are processed rapidly by the first stage, minimizing average latency while maintaining high burst error correcting capacity for problematic packets.
Solution Approach 2:
The patent applies partial error correction in the first stage, correcting only the most critical burst errors rather than attempting to correct all possible errors. This partial action approach reduces processing time for the majority of packets while still providing sufficient reliability, with additional correction applied only when necessary.
Data Source
AI summary
Various examples are provided for encoding for 100G-KR networking. In one example, among others, a coding method uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. In another example, a coding method includes receiving source data from a plurality of physical lanes, combining data from the physical lanes to generate a block, transcoding the block and encoding a data stream including the transcoded block.