10BASE-T1S RX Pulse Coding to Eliminate DME Timing Asymmetry
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Solution Overview
Problem
Existing solutions for reducing timing delays and asymmetries in 10BASE-T1S Ethernet PHYs are impractical due to performance drawbacks and design limitations, particularly in providing sufficient timing margin for PMA sampling and addressing clock speed/tolerance and differential noise on the bus.
Innovation Solution
Implementing a pulse encoding/decoding scheme at the RX pin interface using a return-to-zero (RTZ) coding scheme, where each rising or falling transition on the MDI bus generates an RTZ pulse, eliminating timing asymmetries by processing the output of the receiver comparator at the transceiver circuit and decoding it back to a level scheme for the digital PHY circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If internal PHY circuitry processes receive data with plain NRZ coding, then data transmission is simple, but timing delays and asymmetries reduce timing margin for PMA sampling
Solution Approach 1:
The patent changes the encoding parameter from plain NRZ to pulse-coded NRZ at the RX pin interface. This parameter change transforms the signal representation without fundamentally altering the circuit architecture, thereby reducing timing asymmetries and improving timing margin for PMA sampling while maintaining relative simplicity in the PHY circuit design.
2Loss of time
If existing solutions are implemented to reduce timing delays, then timing margin may be improved, but performance drawbacks and design limitations arise
Solution Approach 1:
The patent introduces pulse encoding/decoding as an intermediary mechanism at the RX pin interface. This intermediary layer transforms the signal format to eliminate timing asymmetries caused by internal PHY circuitry, providing sufficient timing margin for PMA sampling while maintaining robust performance and avoiding the limitations of existing direct timing correction solutions.
3Loss of time
If pulse encoding/decoding is implemented at RX pin interface, then timing asymmetries are eliminated and timing margin is increased, but device complexity increases
Solution Approach 1:
The patent applies pulse encoding/decoding which changes the signal parameter representation rather than requiring complex timing correction circuits. This approach eliminates timing asymmetries and provides sufficient timing margin for PMA sampling while keeping the additional complexity minimal compared to alternative timing correction architectures.
Data Source
AI summary
A 10BASE-T1S PHY method and apparatus are provided for receiving an analog MDI signal conveying DME-encoded data at a receiver comparator to generate a digital output signal, processing the digital output signal using a pulse encoder to generate a pulse-coded output signal with pulses generated at each rising or falling transition in the digital output signal, processing the pulse-coded output signal with an output driver to generate a pulse-coded driver output signal that is transmitted to a receiver interface pin RX, processing the pulse-coded driver output signal with an input comparator to generate a pulse-coded comparator output signal, processing the pulse-coded comparator output signal using a pulse decoder to generate a DME-encoded PMA input signal in which timing asymmetries caused by processing at the receiver comparator and/or output driver have been eliminated, and then processing DME-encoded PMA input signal at a digital PHY circuit in the Ethernet PHY.