10 GbE Transceiver Circuit Integration in Programmable Logic

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Solution Overview

Problem

The integration of 10 GbE PHY layer circuitry in programmable integrated circuit devices is complex and inefficient, requiring numerous components, leading to high power consumption, large space requirements, and increased latency due to complex bus protocols and the need for additional buffers and clock dividers.

Innovation Solution

Implementing a 10 GbE transceiver circuit within the integrated circuit to serialize and deserialize data, allowing programmable circuitry to directly connect to a 10 GbE optical transceiver module, thereby reducing complexity and increasing flexibility by eliminating the need for external specialized PHY layer components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If 10 GbE PHY layer circuitry is implemented using multiple external components (network processor, MAC device, PCS device, optical transceiver), then the system can achieve 10 GbE functionality, but the device complexity and circuit board area increase significantly

Engineering Contradiction:

Improve10 GbE functionalityVSAvoidnumber of components

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the network processor, MAC device, PCS device, and optical transceiver into a single integrated circuit device. The PLD includes integrated 10 GbE PHY layer circuitry that performs functions previously distributed across multiple external components, thereby reducing device complexity while maintaining full 10 GbE functionality.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The integrated circuit device performs multiple functions within a single component. The PLD simultaneously provides programmable logic capabilities and dedicated 10 GbE PHY layer processing, eliminating the need for separate specialized components and reducing overall system complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If 10 GbE PHY layer circuitry is implemented using multiple external components connected via standard interfaces, then the system can achieve 10 GbE functionality, but the circuit board area increases

Engineering Contradiction:

Improve10 GbE functionalityVSAvoidcircuit board area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent integrates functions that were previously distributed across multiple external components into a single integrated circuit device. By combining the network processor, MAC device, PCS device, and optical transceiver capabilities within one PLD, the physical footprint on the circuit board is dramatically reduced while maintaining full 10 GbE functionality.

Inventive Principle:

Principle #5Merging (Combining)

3Speed

If large bus protocols are used to connect optical modules to PLDs, then the system can transmit 10 GbE data, but latency and power consumption increase

Engineering Contradiction:

Improvedata transmission rateVSAvoidlatency

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent extracts the complex bus protocol processing from the PLD by integrating dedicated 10 GbE PHY layer circuitry directly within the PLD. This eliminates the need for large bus protocols to connect external optical modules, thereby reducing latency and power consumption while maintaining 10 GbE data transmission capability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The integrated 10 GbE PHY layer circuitry acts as an intermediary between the PLD's programmable logic and the optical transceiver interface. This intermediary handles the complex protocol processing internally, preventing it from becoming a bottleneck that会增加 latency and power consumption in the data path.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Ease of operation

If additional buffers, clock dividers, and reference clock signals are added to implement bus protocols in PLD, then the system can connect optical modules, but power consumption increases

Engineering Contradiction:

ImproveconnectivityVSAvoidpower consumption

Core Design Contradiction:

Ease of operationVSUse of energy by moving object

Solution Approach 1:

The patent extracts the need for additional buffers, clock dividers, and reference clock signals by integrating the 10 GbE PHY layer circuitry directly within the PLD. This eliminates the requirement for these power-consuming components that would otherwise be needed to implement complex bus protocols for connecting external optical modules.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS8184651B2PLD architecture optimized for 10G Ethernet physical layer solution

Publication Date: 2012.05.22 ALTERA CORP

AI summary

An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10 GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.