10SPE Scrambler Circuit Synchronous Self-Synchronous Data Randomization
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Solution Overview
Problem
Current Ethernet communication standards, particularly 10SPE, face challenges in effectively scrambling payload and preamble data to reduce interference patterns, which can lead to strong tones of interference in network emissions.
Innovation Solution
The implementation of a scrambler and descrambler circuit system that randomizes the data by scrambling both the payload and a portion of the preamble, using synchronization information to ensure proper encoding and decoding, and includes the use of shift registers and specific encoding schemes like 4B5B and DME encoding, allowing for self-synchronous or synchronous scrambling operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data-dependent patterns are transmitted in Ethernet frames, then communication efficiency is maintained, but interference patterns and strong tones are generated in network emissions
Solution Approach 1:
The scrambler circuit uses self-synchronous scrambling where the scrambler itself generates the synchronization information needed for descrambling. The scrambler circuit includes shift registers that automatically generate synchronization bits based on the scrambled data, eliminating the need for separate synchronization mechanisms and maintaining communication efficiency while reducing interference patterns
Solution Approach 2:
The patent applies synchronous and self-synchronous scrambling techniques that change the parameter representation of data. By transforming the data through scrambling operations with synchronization information, the data-dependent patterns are modified in a way that maintains communicative integrity while reducing harmful interference patterns in the transmitted signal
2Object-generated harmful factors
If scrambling is applied to reduce interference patterns, then network emission quality improves, but device complexity increases due to additional scrambler and descrambler circuits
Solution Approach 1:
The patent merges the synchronization information generation and data scrambling functions into a single integrated scrambler circuit. The shift registers within the scrambler circuit simultaneously perform both scrambling operations and synchronization information generation, reducing the need for separate circuits and thereby reducing overall device complexity while maintaining effective interference pattern reduction
Solution Approach 2:
The self-synchronous scrambling mechanism allows the scrambler circuit to generate its own synchronization information internally using shift registers. This self-service approach eliminates the need for external synchronization signals or additional complex synchronization circuits, thereby reducing device complexity while achieving effective pattern reduction
Data Source
AI summary
An apparatus includes an encoder circuit and a scrambler circuit configured to receive a frame, the frame including a preamble and a payload. The scrambler circuit is further configured to scramble contents of the frame including the payload and at least a portion of the preamble, provide synchronization information with results of scrambling the contents, and send results of scrambling the contents to the encoder circuit.