10T SRAM Cell Segmented Pass Transistors
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Solution Overview
Problem
Current graphics processing memory technologies, such as 6T, 8T, and 10T cells, face inefficiencies in power consumption and operational frequency due to complex masking and pre-charging requirements, leading to suboptimal transistor sizing and reduced voltage/power efficiency.
Innovation Solution
A 10T memory cell design with paired access parameter ports allows data storage only when specific pre-determined values are matched, enabling maskable operations without pre-charging, thus optimizing transistor sizing for both read and write operations at lower voltages and higher frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single pair of pass transistors is used for both read and write operations, then device complexity is reduced, but voltage/power efficiency deteriorates due to non-optimal transistor sizing
Solution Approach 1:
The patent divides the single pass transistor pair into two separate pairs: one pair dedicated to read operations and another pair dedicated to write operations. This segmentation allows each pair to be independently optimized for its specific function, with read pass transistors sized for low power consumption during reads and write pass transistors sized for high current delivery during writes, thereby resolving the contradiction between device complexity and voltage/power efficiency
Solution Approach 2:
The patent applies local quality by assigning different transistor sizing characteristics to different pass transistor pairs based on their specific operational requirements. The read pass transistor pair uses smaller transistors optimized for read operations, while the write pass transistor pair uses larger transistors optimized for write operations, allowing each local component to have the optimal properties for its function
2Reliability
If pre-charging is performed for data writing, then data storage reliability is improved, but operational frequency deteriorates due to time consumption
Solution Approach 1:
The patent extracts and eliminates the pre-charging step from the data writing process by using a memory cell configuration that does not require it. The write operation can proceed directly without the time-consuming pre-charging phase, thereby maintaining data storage reliability while significantly improving operational frequency and reducing overall cycle time
Solution Approach 2:
The patent eliminates the need for preliminary pre-charging action by designing the memory cell structure to accept write operations directly. This removes the preliminary step that would otherwise be required before data writing can occur, allowing the memory to operate at higher frequencies while maintaining reliability
3Ease of operation
If pass transistors are sized large for write operations, then write capability is improved, but read stability deteriorates
Solution Approach 1:
The patent segments the pass transistor functionality into two separate pairs, allowing the write pass transistor pair to be sized large for optimal write capability without compromising read stability. The read pass transistor pair can be sized separately for optimal read stability, eliminating the trade-off that exists when a single pair must serve both functions
Solution Approach 2:
The patent applies local quality by optimizing each pass transistor pair independently for its specific function. The write pass transistor pair uses larger transistors optimized for write capability, while the read pass transistor pair uses transistors sized for read stability, allowing each local component to have the optimal properties for its function without compromising the other
4Use of energy by moving object
If operating voltage is decreased, then power consumption is reduced, but operational frequency deteriorates
Solution Approach 1:
The patent segments the memory cell into distinct read and write paths with separate pass transistor pairs, allowing the system to operate at lower voltages for power-efficient read operations while maintaining the capability for high-speed write operations. This segmentation enables the memory to achieve both low power consumption and high operational frequency by using the appropriate path for each operation type
Data Source
AI summary
A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively. The first and second pair of access parameter ports may be adapted to allow access through the first and second pair of access parameter ports if the first access parameter matches a first pre-determined value, and if the second access parameter matches a second pre-determined value.