10T SRAM Vertical Stacking Reduces Area

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Solution Overview

Problem

Current SRAM devices occupy a large area, leading to space wastage due to their size, despite having faster operating speeds than conventional memory devices.

Innovation Solution

The method involves fabricating a semiconductor device with a 10T-SRAM architecture that includes separate levels for read port pull-down and pass-gate devices, allowing for simultaneous read and write operations while optimizing space usage by separating transistors into different levels, specifically placing read port pull-down devices on the lower portion and read port pass-gate devices on the upper portion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional SRAM architecture is used, then fast operating speed is achieved, but large area is occupied

Engineering Contradiction:

Improveoperating speedVSAvoidarea occupied by SRAM device

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar 6T-SRAM architecture to a three-dimensional stacked architecture by forming transistors on different substrates (first substrate and second substrate) separated by an interlayer dielectric. This vertical stacking approach reduces the footprint area while maintaining the necessary transistor count and functionality for fast SRAM operation.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The SRAM device is segmented into multiple independent transistor components formed on separate substrates. The first MOS transistor is formed on the first substrate while the second MOS transistor is formed on the second substrate, allowing parallel fabrication processes and reducing the concentrated area requirement on a single substrate.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If more transistors are added to improve functionality, then device complexity increases, but area occupation increases

Engineering Contradiction:

Improveread and write operation capabilityVSAvoidarea occupied by SRAM device

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent implements a stacked configuration where transistors are arranged vertically across multiple substrates separated by an interlayer dielectric. This three-dimensional arrangement enables complex read and write operations with multiple transistors while reducing the horizontal footprint area, as the transistors occupy the vertical dimension rather than expanding laterally.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11552052B2Static random access memory (SRAM) and method for fabricating the same

Publication Date: 2023.01.10 UNITED MICROELECTRONICS CORP

AI summary

A semiconductor device includes a first metal-oxide semiconductor (MOS) transistor on a first substrate, a first interlayer dielectric (ILD) layer on the first MOS transistor, a second substrate on the first ILD layer, and a second MOS transistor on a second substrate. Preferably, the semiconductor device includes a static random access memory (SRAM) and the SRAM includes a first pull-up device, a second pull-up device, a first pull-down device, a second pull-down device, a first pass-gate device, a second pass-gate device, a read port pull-down device, and a read port pass-gate device, in which the read port pull-down device includes the first MOS transistor and the read port pass-gate device includes the second MOS transistor.