Gate-All-Around CMOS on (110) Substrates for P-Channel Mobility
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving high carrier mobility in transistor structures, particularly with p-channel devices, due to limitations in crystallographic surface orientations, which affect the performance of integrated circuits as they scale down in size.
Innovation Solution
The use of a substrate with a (110) crystallographic surface orientation for forming semiconductor devices, such as nanoribbons and nanosheets, enhances hole mobility in p-channel devices while maintaining or improving overall CMOS performance by optimizing the growth profile of source and drain regions and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional (100) surface orientation substrates are used for forming semiconductor devices, then manufacturing process is well-established, but carrier mobility particularly in p-channel devices is limited
Solution Approach 1:
The patent changes the crystallographic orientation parameter of the substrate from traditional (100) to (110) orientation. This parameter change fundamentally alters the growth profile of semiconductor layers, enabling improved carrier mobility in p-channel devices while maintaining compatibility with existing manufacturing processes through adapted epitaxial growth techniques
2Productivity
If nanowire, nanoribbon or nanosheet architectures are used to maximize semiconductor surface area, then transistor density increases, but carrier mobility deteriorates
Solution Approach 1:
The patent applies local quality by creating specific crystallographic orientations in different regions of the semiconductor structure. The (110) oriented substrate provides optimal growth conditions for high-mobility channels in critical regions, while maintaining the nanosheet architecture for high density elsewhere, thus achieving both high transistor density and high carrier mobility
Solution Approach 2:
The patent employs composite material structures combining silicon nanosheets with carefully engineered (110) oriented epitaxial layers. This composite approach allows the structure to benefit from both the high surface area-to-volume ratio of nanosheets for density and the superior carrier mobility properties of the specific crystallographic orientation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved carrier mobility and performance for both n-channel and p-channel devices, leading to enhanced CMOS architecture with increased hole mobility and effective drain current, overcoming the limitations of traditional (100) surface orientation substrates.
Implementation Method 1
a substrate with a (110) crystallographic surface orientation for forming semiconductor devices, such as nanoribbons and nanosheets, enhances hole mobility in p-channel devices
Data Source
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AI summary
Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.