Gate-All-Around CMOS on (110) Substrates for P-Channel Mobility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in achieving high carrier mobility in transistor structures, particularly with p-channel devices, due to limitations in crystallographic surface orientations, which affect the performance of integrated circuits as they scale down in size.
Innovation Solution
The use of a substrate with a (110) crystallographic surface orientation for forming semiconductor devices, such as nanoribbons and nanosheets, enhances hole mobility in p-channel devices while maintaining or improving overall CMOS performance by adjusting the growth profile of source and drain regions and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional transistor architectures (nanowire, nanoribbon, nanosheet) are used to increase transistor density, then area is reduced and density is improved, but carrier mobility deteriorates
Solution Approach 1:
The patent changes the crystallographic orientation parameter of the substrate from conventional orientations to (110) orientation. This parameter change fundamentally alters the carrier mobility characteristics of the semiconductor material, enabling high hole mobility in p-channel devices while maintaining the compact nanoribbon/nanosheet transistor architectures. The (110) orientation specifically provides enhanced mobility along certain crystal directions, resolving the contradiction between small area and high carrier mobility.
Data Source
AI summary
Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.