16k LDPC Bit Interleaving for Burst-Error-Resistant Decoding
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Solution Overview
Problem
LDPC codes used in digital broadcasting for mobile terminals face challenges in maintaining error resistance due to limited circuit scale and power consumption, requiring reduced decoding load with limited code length and repetitive decoding, which deteriorates performance under burst errors and erasures.
Innovation Solution
The implementation of a decoding apparatus and encoding apparatus that incorporate parity interleave and column twist interleave techniques to improve error resistance by rearranging code bits, allocating more resilient code bits to strong symbol positions and separating error-prone bits, thereby enhancing decoding performance in AWGN channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If code length and repetitive decoding are reduced to decrease decoding load, then power consumption and circuit scale are reduced, but error resistance deteriorates under burst errors and erasures
Solution Approach 1:
The patent applies preliminary action by performing bit interleaving and symbol mapping in advance before transmission. The bit interleaver rearranges code bits to separate error-prone bits, and the symbol mapper assigns bits to symbol positions strategically. This preliminary arrangement ensures that even with reduced code length and repetitive decoding, the system maintains error resistance because the most vulnerable bits are already protected through intelligent positioning before the actual transmission and decoding process.
2Device complexity
If code length and repetitive decoding are reduced to decrease decoding load, then circuit scale is reduced, but error resistance deteriorates under burst errors and erasures
Solution Approach 1:
The patent applies preliminary action by performing bit interleaving and symbol mapping in advance before transmission. The bit interleaver rearranges code bits to separate error-prone bits, and the symbol mapper assigns bits to symbol positions strategically. This preliminary arrangement ensures that even with reduced code length and repetitive decoding, the system maintains error resistance because the most vulnerable bits are already protected through intelligent positioning before the actual transmission and decoding process.
3Device complexity
If simple decoding is used to reduce power consumption and circuit scale, then device complexity is reduced, but performance under burst errors and erasures deteriorates
Solution Approach 1:
The patent applies preliminary action by performing bit interleving and symbol mapping in advance before transmission. The bit interleaver rearranges code bits to separate error-prone bits, and the symbol mapper assigns bits to symbol positions strategically. This preliminary arrangement ensures that even with reduced code length and repetitive decoding, the system maintains error resistance because the most vulnerable bits are already protected through intelligent positioning before the actual transmission and decoding process.
Data Source
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AI summary
The present invention relates to a data processing device and a data processing method capable of improving resistance to error of data. An LDPC encoder 115 encodes by an LDPC code whose code length is 16200 bits and code rate is 4/15, 7/15, or 8/15. A parity check matrix H of the LDPC code is composed by arrangement of an element 1 of an information matrix determined by a parity check matrix initial value table indicating a position of the element 1 of the information matrix corresponding to an information length corresponding to the code length and the code rate for each 360 columns of the parity check matrix H with a period of 360 columns in a column direction. The parity check matrix initial value table is for digital broadcasting for a mobile terminal, for example. This technology may be applied to a case in which LDPC encoding and LDPC decoding are performed.