16QAM Bit Permutation for DVB-S2 LDPC Error Tolerance
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Solution Overview
Problem
In digital broadcasting for portable terminals, existing LDPC code decoding methods require reduced circuit scale and power consumption, necessitating restricted code length and repetition decoding, while maintaining error tolerance, which is challenging due to burst errors and erasures in AWGN communication paths.
Innovation Solution
A data processing device and method that performs LDPC encoding with a code length of 16200 bits and encoding rates of 1/3 or 2/5, using a parity check matrix with specific configurations, and interchanges code bits with symbol bits corresponding to 16QAM signal points to enhance error tolerance by allocating weak code bits to strong symbol bits, thereby improving decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If code length and repetition decoding are restricted to reduce circuit scale and power consumption, then device complexity and energy use are reduced, but error tolerance deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the treatment of code bits based on their error susceptibility. Weak code bits (more prone to errors) are identified and specifically protected by mapping them to strong symbol bits (those with higher error tolerance in the modulation scheme), while strong code bits are mapped to weak symbol bits. This localized differentiation optimizes error protection where most needed without requiring increased overall system complexity.
Solution Approach 2:
The patent changes the mapping parameter between code bits and symbol bits to optimize error tolerance. By using a specific bit interchange pattern that maps weak code bits to strong symbol bits, the system achieves improved error performance without changing the code length or repetition decoding parameters, thus maintaining low device complexity while enhancing reliability.
2Use of energy by moving object
If code length and repetition decoding are restricted to reduce power consumption, then energy use is reduced, but error tolerance deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the treatment of code bits based on their error susceptibility. Weak code bits (more prone to errors) are identified and specifically protected by mapping them to strong symbol bits (those with higher error tolerance in the modulation scheme), while strong code bits are mapped to weak symbol bits. This localized differentiation optimizes error protection where most needed without requiring increased overall system complexity.
Solution Approach 2:
The patent changes the mapping parameter between code bits and symbol bits to optimize error tolerance. By using a specific bit interchange pattern that maps weak code bits to strong symbol bits, the system achieves improved error performance without changing the code length or repetition decoding parameters, thus maintaining low device complexity while enhancing reliability.
3Reliability
If bit allocation is optimized to improve error tolerance, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by differentiating the treatment of code bits based on their error susceptibility. Weak code bits (more prone to errors) are identified and specifically protected by mapping them to strong symbol bits (those with higher error tolerance in the modulation scheme), while strong code bits are mapped to weak symbol bits. This localized differentiation optimizes error protection where most needed without requiring increased overall system complexity.
Solution Approach 2:
The patent changes the mapping parameter between code bits and symbol bits to optimize error tolerance. By using a specific bit interchange pattern that maps weak code bits to strong symbol bits, the system achieves improved error performance without changing the code length or repetition decoding parameters, thus maintaining low device complexity while enhancing reliability.
Data Source
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AI summary
The present technology relates to a data processing device (11) and a data processing method that enable tolerance against error of data to be improved. In the case in which an DVB-S2 LDPC codeword of length 16200 bits and rate 2/5 is modulated by 16QAM, an interchange unit (32) sets a (#i + 1)-th code bit from a most significant bit of eight code bits as a bit b#i, 0 < i < 7, and allocates code bits b0, b1, b2, b3, b4, b5, b6, and b7 to symbol bits y7, y5, y4, y0, y3, y1, y2, and y6, respectively, wherein the eight symbol bits y#i form two consecutive 16QAM symbols. The present invention can be applied to a DVB transmission system transmitting an LDPC code.