19-12 Binary-Ternary LUT Mapping for Low-Error Flash Memory
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Solution Overview
Problem
Existing binary to ternary mapping schemes in multi-level flash memory suffer from error propagation and require complex hardware implementations, leading to inefficiencies in error correction and storage density.
Innovation Solution
A 19-12 mapping using look-up tables (LUTs) is implemented to efficiently convert binary data to ternary and back, reducing the complexity of hardware requirements and achieving closer storage density to the theoretical limit of 1.5849 bits per cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If typical binary to ternary mapping is used to achieve high storage density in multi-level flash memory, then storage density approaches the theoretical limit, but error propagation increases significantly
Solution Approach 1:
The patent segments the binary-to-ternary mapping process into multiple independent stages using a tree-based structure. Instead of directly mapping all binary bits to ternary symbols in one step, the mapping is divided into hierarchical levels where intermediate results are computed and stored. This segmentation isolates error propagation to individual segments, preventing cascading errors across the entire data set while maintaining high storage density.
Solution Approach 2:
The patent performs preliminary computations and pre-calculates mapping relationships during the encoding phase, storing intermediate results in a structured format. By preparing and storing these preliminary mapping results before actual data storage, the system reduces the complexity of error correction during read operations and minimizes error propagation while achieving near-theoretical storage density.
2Quantity of substance
If complex mapping algorithms are implemented to achieve optimal storage density, then storage efficiency improves, but hardware complexity increases
Solution Approach 1:
The complex mapping algorithm is segmented into modular computational stages implemented as separate hardware units. Each stage handles a specific portion of the mapping process, allowing for optimized resource utilization and reduced inter-stage data transfer. This modular segmentation maintains high storage efficiency while managing hardware complexity through structured organization.
Solution Approach 2:
The patent transforms the computational problem from a two-dimensional binary-to-ternary direct mapping into a multi-dimensional hierarchical structure. By introducing intermediate representation layers and using a tree-based organization, the system achieves optimal storage density through dimensionality expansion while keeping individual hardware components relatively simple and manageable.
3Ease of manufacture
If direct binary to ternary conversion is used for simplicity, then hardware implementation is easier, but storage density is suboptimal
Solution Approach 1:
The patent segments the conversion process into standardized modular units that can be independently implemented and tested. This segmentation makes the complex high-density mapping approach as manufacturable as simple direct conversion, since each module can be verified independently and assembled systematically, achieving both ease of manufacture and optimal storage density.
Solution Approach 2:
The system performs preliminary organization of mapping relationships during manufacturing setup, pre-configuring the hierarchical structure and intermediate tables. This preliminary action simplifies the actual runtime conversion operations, making the hardware implementation as straightforward as simple direct conversion while achieving superior storage density through the pre-optimized structure.
Data Source
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AI summary
Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.