1D-2R Memory Cell Architecture for Sneak Path Suppression
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Solution Overview
Problem
Current non-volatile memory devices, such as RRAM, face limitations in cost and performance, particularly due to sneak paths in 3D crosspoint memory arrays, which restrict block size and increase manufacturing costs, making them unsuitable for primary storage in electronic products.
Innovation Solution
A one diode, two resistive element (1D-2R) memory cell architecture is introduced, comprising a switching element and two resistive memory elements with complementary polarities, which are electrically coupled to bit and word lines, allowing for improved selectivity and reduced sneak paths through the use of polysilicon diodes and specific lithography steps to form the memory cell components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D crosspoint memory arrays are used to increase storage density, then storage capacity is improved, but sneak paths increase causing higher leakage and reduced reliability
Solution Approach 1:
A select device (diode or transistor) is introduced as an intermediary component between the bit line and the RRAM memory elements. This intermediary actively controls current flow, enabling reliable selection of specific memory cells during read and program operations while blocking sneak paths that would otherwise cause leakage and data retention issues in 3D crosspoint arrays.
2Reliability
If select devices are added to eliminate sneak paths, then reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent employs simple diode structures formed through standard semiconductor fabrication processes as select devices. These diodes provide effective sneak path suppression with minimal added complexity, using basic p-n junction physics rather than complex transistor gates or multi-layer structures, thereby maintaining manufacturing simplicity while achieving the desired reliability improvement.
3Ease of manufacture
If block size is reduced to manage sneak paths, then manufacturing cost is improved, but storage density decreases
Solution Approach 1:
The select device acts as an intermediary that enables larger block sizes by actively suppressing sneak paths. With reliable cell selection, the memory array can be organized into larger blocks without suffering from uncontrolled leakage, allowing increased storage density while maintaining manufacturability through standard fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 1D-2R memory cell architecture enhances the performance and reduces manufacturing costs by enabling efficient programming, reading, and erasing operations, with minimal leakage and high resistance states, thereby improving the suitability of RRAM for primary storage applications.
Implementation Method 1
These unipolar diodes, however, cannot service popular bipolar RRAM memory devices
Implementation Method 2
Each layer may comprise an array of RRAM memory elements
Data Source
AI summary
A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element, and a two-terminal switching element. The first resistive memory element is electrically coupled to the second resistive memory element and to the switching element at a common node.