1D Offset Correction for Semiconductor Inspection Alignment
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Solution Overview
Problem
Current semiconductor inspection methods face challenges in accurately aligning and inspecting devices with unique structures in only one dimension, leading to reduced coordinate accuracy and increased nuisance events due to the need for large care areas.
Innovation Solution
A system and method that utilize a processor to determine one-dimensional (1D) offset corrections for care areas, enabling the identification of 1D unique targets and performing 1D alignment to improve inspection accuracy, allowing for reduced care area sizes and increased sensitivity by using 1D unique targets for alignment, even if structures lack unique features in one direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If 2D unique targets are required for PDA alignment, then alignment accuracy is improved, but inspection capability for memory devices with only 1D unique structures is lost
Solution Approach 1:
The patent segments the alignment problem into two independent 1D alignment tasks (X-direction and Y-direction) instead of requiring a single 2D alignment. This allows the system to perform PDA alignment using only 1D unique targets in either direction, making memory devices with 1D unique structures inspectable while maintaining alignment accuracy.
2Reliability
If legacy care areas with buffer around structures are used, then defect coverage is improved, but sensitivity is lost and nuisance events increase
Solution Approach 1:
The patent performs 1D offset correction in advance to precisely determine the location of care areas before inspection. By calculating the offset between design coordinates and actual image coordinates using 1D unique targets, the system can place care areas with zero or minimal borders, eliminating the need for large legacy care area buffers while maintaining complete defect coverage.
3Reliability
If large legacy care areas are used to ensure defect coverage, then reliability is improved, but coordinate accuracy and defect location precision deteriorate
Solution Approach 1:
The system performs 1D offset correction before defect inspection to accurately locate care areas. By determining the offset between design and actual image coordinates in advance, the system can define precise care area boundaries with minimal borders, ensuring complete defect coverage without sacrificing location accuracy.
Solution Approach 2:
The patent applies different border strategies to different dimensions: zero or minimal borders in dimensions with 1D unique targets (where high precision is achieved) and appropriate borders only where needed. This localized approach to care area definition maintains reliability while improving precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances inspection sensitivity by an order of magnitude, reduces nuisance events, and enables precise placement of care areas, improving decision-making capabilities for semiconductor manufacturers, particularly for memory devices with narrow care areas.
Implementation Method 1
an energy source that generates an energy beam, a stage configured to secure a wafer in a path of the energy beam, and a detector that receives the energy beam reflected from the wafer
Data Source
AI summary
Care areas for a first image of a die can be determined according to a 1D offset correction. The 1D offset correction can be based on 1D offsets between the first image and a second image for each of the image frames and also can be based on 1D offsets between a design and the second image for each of the image frames. The care areas can have a zero border for a dimension that is aligned to the design and a legacy border for the other dimension.