1T DRAM With Partial Insulating Layers For Carrier Confinement
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Solution Overview
Problem
1T DRAM devices face challenges in maximizing retention time and operation reliability due to carrier loss beyond energy barriers in p-n junctions, especially at high temperatures, where hold voltage is always required.
Innovation Solution
A 1T DRAM device with a partial insulating layer structure, featuring source and drain regions connected by multiple pn junctions and surrounded by gates with a gate insulating layer, and additional partial insulating layers between regions to reduce carrier loss by forming high energy barriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-n junction structure is used in 1T DRAM, then the device can store electrons and holes in energy wells, but carrier leakage occurs beyond the energy barrier especially at high temperatures
Solution Approach 1:
The body region is divided into multiple doped semiconductor layers (first doped layer, second doped layer, third doped layer) separated by partial insulating layers, creating multiple pn junctions. This segmentation creates additional energy barriers that prevent carrier leakage while maintaining the energy well structure for storing carriers.
Solution Approach 2:
Partial insulating layers are introduced as intermediary elements between the doped semiconductor layers. These insulating layers form high energy barriers that block carrier leakage while allowing the pn junctions to maintain their charge storage function. The insulating layers act as mediators that prevent direct carrier transport between adjacent doped regions.
2Reliability
If hold voltage is applied continuously to maintain data, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The device structure is designed with multiple pn junctions and partial insulating layers that create high energy barriers during fabrication. This preliminary structural configuration ensures that carriers are naturally confined without requiring continuous hold voltage, thereby maintaining data integrity while reducing power consumption during operation.
Solution Approach 2:
The patent converts the potential harm of carrier leakage into a benefit by using the same pn junction structure to create energy barriers. The pn junctions that could potentially allow carrier loss are configured to create deep energy wells and barriers, where the junction itself becomes the mechanism for preventing carrier leakage rather than causing it.
3Reliability
If multiple doped semiconductor layers with pn junctions are used, then carrier leakage is reduced, but device structure becomes more complex
Solution Approach 1:
Partial insulating layers are selectively positioned only at specific interfaces between doped semiconductor layers where carrier leakage is most problematic. The insulating layers are not applied uniformly throughout the entire device but only at critical locations, maintaining structural simplicity while providing targeted protection against carrier leakage.
Solution Approach 2:
The device structure combines different materials (doped semiconductor layers and insulating layers) to create a composite structure. This composite approach allows the device to leverage the beneficial properties of each material type - the semiconductor layers provide carrier storage capability while the insulating layers provide barrier functionality - without requiring a single complex material solution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The partial insulating layers enhance retention time and operation reliability by minimizing carrier leakage, allowing the device to maintain data integrity even at high temperatures without constant hold voltage.
Implementation Method 1
minimizing carrier leakage, allowing the device to maintain data integrity even at high temperatures without constant hold voltage
Implementation Method 2
electron-hole pairs are generated by a high-energy carrier collision or an interband tunneling operation near the drain region
Data Source
AI summary
A feedback 1T DRAM device that has a partial insulating film structure is provided. A body region may be divided into two or more in a channel direction by pn junctions and/or partial insulating layers, and gates may be formed on each of the divided body regions. The present invention can be operated by filling and subtracting electrons in the energy well of the conduction band and holes in the energy well of the valence band, respectively. In addition, it is possible to maximize retention time and improve operation reliability by reducing carrier loss by energy barriers of pn junctions and/or partial insulating layers.