1T-Memory Device Using P-N-I-N Nanostructure for Low Power Synapse
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Solution Overview
Problem
Conventional silicon CMOS process-based synapse devices face challenges in miniaturization, integration, and power efficiency due to the need for multiple transistors, high power consumption, and limited read sensing margins, while existing memristor devices are not compatible with silicon CMOS processes and require separate memory and processor units, leading to inefficiencies like the von Neumann bottleneck.
Innovation Solution
A 1T-memory device with a p-n-i-n nanostructure that operates using a positive feedback loop mechanism, allowing for both memory and switching functions with reduced power consumption and increased integration, utilizing a single transistor and requiring lower applied voltages for write/erase operations, thus enabling miniaturization and efficient read sensing even in narrow memory windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional 6T-SRAM structure is used, then memory function is achieved, but device area and power consumption increase
Solution Approach 1:
The patent merges the memory function and switching function into a single 1T device structure, eliminating the need for separate 6T-SRAM cells. This consolidation reduces device area while maintaining memory functionality through the unique p-n-i-n nanostructure that provides both storage and switching capabilities in one integrated component.
Solution Approach 2:
The 1T-memory device achieves multi-functionality by simultaneously providing memory storage, switching, and sensing capabilities within a single device structure. The p-n-i-n nanostructure enables the device to perform multiple functions that traditionally required separate components, thereby reducing overall device area and improving integration.
2Reliability
If a conventional 6T-SRAM structure is used, then memory function is achieved, but power consumption increases
Solution Approach 1:
By merging memory and switching functions into a single 1T device, the patent eliminates redundant transistor operations and reduces overall power consumption. The integrated structure reduces leakage current and energy dissipation associated with multiple transistor switches, achieving lower power consumption while maintaining full memory functionality.
Solution Approach 2:
The patent extracts and eliminates unnecessary components (four additional transistors) from the conventional 6T-SRAM structure, retaining only the essential memory function in a 1T configuration. This extraction removes sources of power consumption associated with extra transistors while preserving core memory operations.
3Reliability
If a conventional thyristor DRAM is used, then memory operation is achieved, but read sensing margin is insufficient
Solution Approach 1:
The patent applies local quality optimization by engineering specific regions within the p-n-i-n nanostructure to enhance read sensing capability. The barrier region and intrinsic region are specifically designed to provide localized properties that improve current modulation and sensing margin, addressing the insufficient read sensing margin while maintaining overall memory operation.
Solution Approach 2:
The patent employs parameter changes in the p-n-i-n nanostructure, specifically adjusting doping concentrations, region widths, and material compositions to optimize read sensing margin. By modifying these physical parameters, the device achieves improved current differentiation between stored states, enabling sufficient read sensing margin while maintaining reliable memory operation.
4Adaptability or versatility
If memristor synapse devices are used, then synapse function is achieved, but compatibility with silicon CMOS process is lost
Solution Approach 1:
The patent uses parameter changes by adapting the p-n-i-n nanostructure to operate within conventional silicon CMOS process parameters. By adjusting doping levels, region dimensions, and material properties to match standard CMOS fabrication capabilities, the device achieves synapse functionality while maintaining full compatibility with existing silicon CMOS manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 1T-memory device achieves improved processing speed, reduced power consumption, and enhanced integration by converging memory and switching functions in a single device, overcoming the limitations of conventional SRAM and memristor devices, and enabling efficient operation in a selective volatile mode.
Implementation Method 1
the positive feedback loop mechanism of a p-n-i-n nanostructure device
Implementation Method 2
hysteresis characteristics on an IDS-VGS characteristic curve are used as a memory
Data Source
AI summary
A semiconductor device includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region. The semiconductor device may operate as a switch or a volatile memory according to a gate voltage applied to a gate and a drain voltage applied to a drain.