1T SRAM Floating Body Transistor Amorphized Substrate
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Solution Overview
Problem
Current methods for manufacturing floating body RAM (FBRAM) devices face limitations in manufacturing costs, operation voltage, and data retention period, necessitating improved and cost-effective solutions for volatile memory devices.
Innovation Solution
A volatile memory device is designed with a substrate having an amorphized isolation buffer layer and a transistor with a floating body, where the isolation buffer layer is formed by amorphizing a portion of the substrate, reducing substrate leakage and manufacturing costs, and improving data retention and memory cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DRAM or SRAM structures are used, then fast operation is achieved, but packing density is limited
Solution Approach 1:
The patent changes the physical state of the substrate portion from crystalline to amorphous by controlling the amorphization process parameters (ion implantation energy, dose, temperature). This parameter change creates the isolation buffer layer that enables floating body transistor operation, achieving both fast operation and high packing density through the novel structural configuration
Solution Approach 2:
The patent creates a composite structure combining crystalline substrate regions with amorphous isolation buffer layers. This composite material approach allows the device to maintain the electrical properties needed for fast operation while achieving higher packing density through the compact floating body transistor design
2Area of stationary object
If FBRAM is manufactured using current process methods, then high packing density is achieved, but manufacturing cost increases
Solution Approach 1:
The patent uses the substrate itself as a disposable resource by amorphizing portions of it to create isolation buffers. This eliminates the need for separate isolation materials and reduces manufacturing steps, thereby lowering manufacturing cost while maintaining high packing density
Solution Approach 2:
The amorphized substrate portion serves multiple functions: it acts as both the isolation buffer layer and the source of charge carriers for the floating body transistor. This multi-functionality reduces the number of separate components needed, simplifying manufacturing and reducing costs
3Area of stationary object
If FBRAM is manufactured using current process methods, then high packing density is achieved, but data retention period decreases
Solution Approach 1:
The patent applies local quality by creating amorphous regions specifically at the isolation buffer locations while maintaining crystalline structure in the active transistor regions. This localized amorphization reduces substrate leakage at critical interfaces without affecting the operational properties of the floating body transistors, thereby improving data retention while maintaining high packing density
4Object-generated harmful factors
If amorphized isolation buffer layer is used, then substrate leakage is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent extracts the isolation buffer function from separate material layers and integrates it directly into the substrate by amorphizing substrate portions. This extraction and integration approach reduces the number of manufacturing steps compared to depositing separate isolation layers, thereby reducing process complexity while effectively reducing substrate leakage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces manufacturing costs, enhances data retention, and improves memory cell performance by using an amorphized substrate isolation buffer layer and a band engineered floating body, achieving better retention time and reduced charge leakage.
Implementation Method 1
The isolation buffer layer is an amorphized portion of the substrate
Data Source
AI summary
One-transistor (1T) volatile memory devices and manufacturing methods thereof are provided. The device includes a substrate having top and bottom surfaces and an isolation buffer layer disposed below the top substrate surface. The isolation buffer layer is an amorphized portion of the substrate. An area of the substrate between the isolation buffer layer and the top substrate surface serves as a body region of a transistor. The device also includes a transistor disposed over the substrate. The transistor includes a gate disposed on the top substrate surface, and first and second diffusion regions disposed in the body region adjacent to first and second sides of the gate.