1T1D DRAM Cell Using Diode Depletion Capacitance
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Solution Overview
Problem
Current semiconductor process technologies for implementing SRAM and DRAM face challenges with high transistor count, power consumption, and access circuit complexity, leading to poor performance and increased access time, which affects CPU operations and memory hierarchy efficiency.
Innovation Solution
The use of standard semiconductor process technology to create DRAM with a structure consisting of one transistor and one diode, leveraging depletion capacitance to form a capacitor, and cooperating with access circuits to enhance performance, reduce transistor count, and lower power consumption, while aiming to replace or enhance DRAM with SRAM to minimize cache memory hierarchy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SRAM structures (6T, 5T, 4T) are used, then storage stability is improved, but transistor count and device complexity increase
Solution Approach 1:
The patent extracts the capacitor component from the traditional SRAM structure and replaces it with a diode, utilizing the diode's depletion capacitance. This removes unnecessary components while retaining the essential storage function, thereby reducing transistor count from 6T/5T/4T to a more efficient configuration without compromising storage stability.
Solution Approach 2:
The patent changes the physical parameter of the diode by utilizing its depletion capacitance characteristic. By operating the diode in depletion mode and controlling the depletion region width through voltage application, the patent creates an effective capacitor without requiring a separate capacitor component, thus simplifying the overall structure.
2Device complexity
If DRAM with 1T1C structure is used, then transistor count is reduced, but access time increases and power consumption increases due to refreshing requirements
Solution Approach 1:
The patent segments the memory access operation into distinct phases using the spread pulse trigger mechanism. The trigger circuit divides the access cycle into initialization, storage, and readout phases, allowing for optimized timing in each phase. This segmentation enables faster overall access by preventing bottlenecks in any single operation phase.
Solution Approach 2:
The patent employs periodic pulse signals from the spread pulse trigger to control the timing of write and read operations. The periodic nature of these triggers ensures synchronized operation of access transistors and maintains optimal timing relationships, reducing access time compared to continuous or irregular signaling methods.
3Device complexity
If DRAM is used instead of SRAM, then device complexity is reduced, but power consumption increases due to continuous refreshing
Solution Approach 1:
The patent implements a self-service mechanism where the diode's depletion capacitance automatically maintains the stored charge without requiring external refresh operations. The depletion region naturally replenishes charge through the diode's physical characteristics, eliminating the need for power-consuming refresh cycles that are mandatory in traditional DRAM systems.
4Speed
If cache memory hierarchy is expanded to reduce CPU access time, then speed is improved, but device complexity and area increase
Solution Approach 1:
The patent creates a universal memory cell design that combines the fast access characteristics of SRAM with the density of DRAM. The 1T1D structure can function as both static and dynamic memory depending on operating conditions, eliminating the need for separate cache hierarchies and reducing overall system complexity while maintaining high speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of transistors in SRAM, improves storage stability, decreases power consumption, and enhances access time, allowing for more efficient CPU operations and reduced cache memory requirements, thereby improving overall memory performance.
Implementation Method 1
the depletion capacitance of diode is utilized to form a capacitor
Data Source
AI summary
The beginning of using Complementary Metal-Oxide-Semiconductor (CMOS) process technology to implement Static Random-Access Memory (SRAM) which transistor number is six. And then reducing transistor number for increasing integration density, but it will diminish the stability of memory, and also may enhance the complexity of access circuit, thus increasing the power consumption. For increasing the integration density of SRAM, and according to the electrical characteristics of reduced transistor number therefore designing the memory possess low power consumption and its corresponding circuits, and then implementing an access system. If electrical characteristic of the other various memories are similar to SRAM, such as Dynamic Random-Access Memory (DRAM), so they can also use the corresponding access circuit of SRAM.