1T1D OTP Memory Cell for Low-Voltage Programming

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Solution Overview

Problem

Conventional one-time programmable (OTP) memories, such as 1T1R, 1T1C, and 1T1T, require large areas and high voltages (4-5V) for programming, necessitating additional peripheral circuits that further increase area requirements.

Innovation Solution

A 1-transistor-1-diode (1T1D) OTP memory design using an OTP diode and a control field effect transistor (FET), which operates with a low programming voltage (around 3V) and avoids the need for high voltage generation circuits, reducing the overall area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If conventional 1T1R, 1T1C, or 1T1T OTP memory structures are used, then programming functionality is achieved, but large area is required due to long conductive liners, wide metallic pads, or additional peripheral circuits

Engineering Contradiction:
Improvememory cell areaVSAvoidstructure complexity
Core Design Contradiction:
Area of moving objectVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the unnecessary high voltage generation peripheral circuits from the memory system. By using a 1T1D structure with avalanche breakdown mechanism, the patent removes the need for separate high voltage generation circuits that were required in 1T1C and 1T1T structures, thereby reducing overall device area and complexity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the programming function and storage function into a single integrated 1T1D cell structure. The control FET and OTP diode work together as a unified cell, eliminating the need for separate high voltage generation circuits and reducing both area and complexity compared to conventional separate-function designs

Inventive Principle:
Principle #5Merging (Combining)

2Ease of manufacture

If high voltage (4-5V) is applied to break down oxide layer in capacitor or gate oxide layer in storage transistor, then programming is enabled, but additional peripheral circuits are required which increase area

Engineering Contradiction:
Improveprogramming capabilityVSAvoidperipheral circuit area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent changes the programming mechanism from high voltage breakdown (4-5V) to low voltage avalanche breakdown (around 3V). This parameter change in operating voltage eliminates the need for high voltage generation peripheral circuits, reducing area while maintaining programming capability through the avalanche breakdown of the OTP diode

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The OTP diode structure inherently provides the high voltage breakdown function through its avalanche breakdown mechanism at low voltage. The diode structure itself serves the dual purpose of both storage and programming, eliminating the need for external high voltage generation circuits and peripheral components

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The 1T1D design achieves high stability and a smaller peripheral circuit area, requiring only a low programming voltage and eliminating the need for additional high-voltage generation circuits.

Implementation Method 1

applying a programming voltage to a bit line makes an avalanche breakdown occur in the OTP diode, thereby forming a programmed state of the OTP diode

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS12525307B2One-time programmable memory circuit, one-time programmable memory and operation method thereof
Publication Date: 2026.01.13 ERAYTRONIKS CO LTD
  • US12525307B2 patent drawing
  • US12525307B2 patent drawing
  • US12525307B2 patent drawing

AI summary

The present disclosure provides a one-time programmable memory, which includes a one-time programmable (OTP) diode and a control field effect transistor (FET). One end of the OTP diode is electrically connected to a source line. The control FET includes a gate, a first source/drain and a second source/drain, the gate of the control FET is electrically connected to a word line, the first source/drain of the control FET is electrically connected to a bit line, and the second source/drain of the control FET is electrically connected to another of the OTP diode.