1T1R Computing Array for In-Memory Boolean Logic Cascading
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Solution Overview
Problem
The existing computing architectures, particularly the von Neumann architecture, face challenges in achieving superior computing power due to the separation of storage and computation, and existing RRAM technologies struggle to implement complex computing functions and circuit cascading in 1T1R device structures.
Innovation Solution
A computing array based on 1T1R devices, comprising 1T1R arrays and peripheral circuits, that utilize resistive states to perform Boolean logic operations, allowing for the storage and processing of information through reversible resistance changes, enabling complex computing functions and circuit integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional von Neumann architecture is used, then storage and computation are separated, but computing power is limited due to the bottleneck problem
Solution Approach 1:
The patent merges storage and computation functions into a unified crossbar array architecture where RRAM devices simultaneously serve as storage elements and computing units. The conductive states of RRAM cells enable both data storage and in-memory computing operations, eliminating the von Neumann bottleneck by allowing computation to occur directly within the storage array.
Solution Approach 2:
The RRAM-based crossbar array provides multi-functionality by enabling various computing operations (Boolean logic, neural network inference, linear algebra operations) using the same hardware structure. The universal computing-in-memory platform can perform different computational tasks by configuring the crossbar array with appropriate weight values and applying different input patterns.
2Adaptability or versatility
If existing RRAM technology is applied in 1T1R structure, then low power consumption and high speed are achieved, but complex computing functions and circuit cascading cannot be realized
Solution Approach 1:
The patent segments the computing array into multiple independently controllable banks or regions, each capable of performing computing operations. This segmentation enables complex computing functions by dividing large-scale computations into smaller sub-tasks that can be executed in parallel across different segments, while also facilitating circuit cascading through standardized interconnect interfaces between segments.
Solution Approach 2:
The patent transitions from planar 2D crossbar arrays to 3D vertically-stacked crossbar architectures, adding a vertical dimension to the computing array. This dimensional expansion increases the density of storage and computing elements while enabling more complex computing functions through multi-layer interconnect structures and three-dimensional data representations.
3Device complexity
If back-to-back RRAM structure is used, then non-volatile Boolean logic operations are realized, but circuit integration and complex computing functions are limited
Solution Approach 1:
The patent applies preliminary action by pre-configuring the RRAM crossbar array with synaptic weights and biases before computing operations. This pre-programming of the array with computational parameters enables the hardware to perform complex computing functions directly during operation, eliminating the need for extensive circuit integration and complex control logic that would otherwise be required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the implementation of a complete set of non-volatile Boolean logic operations, simplifies operation methods, and enhances compatibility, allowing for direct storage of calculated results, thereby reducing circuit complexity and improving computing capabilities.
Implementation Method 1
resistive element has a stacked structure with a nonvolatile resistance transition characteristic... with the stimulation of an applied signal, the resistance state of the 1T1R device can be transformed from High Resistance to Low Resistance
Data Source
AI summary
The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.