1T1R Hamming Weight Calculation Using Resistive Memory Currents
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for calculating Hamming weight in digital circuits require a large number of full-adders and half-adders, resulting in a large circuit scale and high power consumption.
Innovation Solution
A Hamming weight calculation method based on a one-memory one-transistor (1T1R) structure, where a controller adjusts the gate voltage of a transistor and the resistance state of a memory to determine the Hamming weight of a binary sequence without needing a large quantity of full-adders and half-adders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional POPCNT instruction is implemented using full-adders and half-adders, then Hamming weight calculation can be performed, but circuit scale becomes large and power consumption increases
Solution Approach 1:
The patent replaces the conventional mechanical/circuit-based adder system with a resistive memory-based system that uses resistance states to represent binary values. Instead of using full-adders and half-adders to compute Hamming weight, the invention uses a population of resistive memory cells where each cell's resistance state (high or low) directly represents a bit value, and the total current through the memory array provides the Hamming weight result, eliminating the need for complex combinatorial logic circuits.
Solution Approach 2:
The patent changes the fundamental parameter representation from voltage-based logic levels in conventional circuits to resistance-based states in resistive memory. By using resistance as the primary parameter to store and process binary information, the system achieves parallel processing capability where all bits are evaluated simultaneously through the memory array's total current, rather than sequentially through multiple stages of adders.
2Productivity
If conventional POPCNT instruction is implemented using full-adders and half-adders, then Hamming weight calculation can be performed, but power consumption becomes high
Solution Approach 1:
The patent replaces the conventional mechanical/circuit-based adder system with a resistive memory-based system that uses resistance states to represent binary values. Instead of using full-adders and half-adders to compute Hamming weight, the invention uses a population of resistive memory cells where each cell's resistance state (high or low) directly represents a bit value, and the total current through the memory array provides the Hamming weight result, eliminating the need for complex combinatorial logic circuits.
Solution Approach 2:
The patent enables continuous parallel processing by maintaining the memory cells in their resistance states representing the binary data, allowing the Hamming weight to be read out continuously as the total current without requiring multiple discrete calculation cycles through sequential adder stages.
3Device complexity
If 1T1R structure is used for Hamming weight calculation, then circuit scale is reduced and power consumption is lowered, but the method requires precise control of transistor gate voltage and memory resistance states
Solution Approach 1:
The patent makes the resistive memory cells multi-functional by using them both for data storage (maintaining resistance states representing binary values) and for computation (the total current through the array directly gives the Hamming weight). This eliminates the need for separate storage and computation units, reducing overall circuit complexity while the control logic handles the precision requirements through standardized voltage levels for setting and reading resistance states.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the circuit scale and power consumption while enabling efficient Hamming weight calculation by controlling the on-off state of a transistor and resistance state of a memory to determine the Hamming weight through output currents.
Implementation Method 1
a controller, in signal connection with the first operation unit... determines a Hamming weight of first bit data in an input first binary sequence based on a first output current on a source of the first transistor
Implementation Method 2
controls a target resistance state of the first memory based on the on-off state of the first transistor. When the first transistor is in the on state, the target resistance state of the first memory is a high resistance state; and when the first transistor is in the off state, the target resistance state of the first transistor is a low resistance state
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
Embodiments of this application disclose a Hamming weight calculation method based on an operation apparatus. The operation apparatus in this application includes a controller and a first operation unit, the controller is in signal connection with the first operation unit, the first operation unit includes a first memory and a first transistor, a drain of the first transistor is connected to a negative electrode of the first memory, and a source of the first transistor is grounded. The Hamming weight calculation method is performed by the controller. Specifically, the controller sets an initial resistance state of the first memory to a low resistance state; determines a first gate voltage of the first transistor based on first bit data in an input first binary sequence, and control an on-off state of the first transistor based on the first gate voltage; controls a target resistance state of the first memory based on the on-off state of the first transistor; and determines a Hamming weight of the first bit data based on a first output current on the source of the first transistor.