1T1R Memory Max Pooling Processor for Neural Network Efficiency

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Solution Overview

Problem

Existing convolutional neural network processors face high power consumption and time consumption due to large data transmission between the processor and memory, particularly in convolutional and pooling layers, which is known as the Von Neumann bottleneck.

Innovation Solution

A max pooling processor based on 1T1R memory, where one transistor is connected in series with a RRAM, utilizes the non-volatile multi-valued conductance regulation characteristic of RRAM to perform max pooling operations, directly storing results and reducing data interaction between storage and computation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data transmission between processor and memory is performed using conventional processors (CPU/GPU), then computation can be performed, but power consumption and time consumption increase due to the Von Neumann bottleneck

Engineering Contradiction:
Improvecomputation speedVSAvoiddata transmission time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent merges the computation and storage functions into a single integrated structure by connecting RRAM devices directly to the processing circuitry. The RRAM array serves as both the storage medium for intermediate data and the computational element for pooling operations, eliminating the need for separate data transmission between processor and memory.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces RRAM devices as an intermediary between traditional processors and memory systems. These RRAM-based max pooling operation modules act as intermediate processing units that can perform computation locally on stored data, reducing the frequency and volume of data transfers to and from main memory.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If data transmission between processor and memory is performed using conventional processors (CPU/GPU), then computation can be performed, but power consumption increases due to the Von Neumann bottleneck

Engineering Contradiction:
Improvecomputation capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent merges the computation and storage functions into a single integrated structure by connecting RRAM devices directly to the processing circuitry. The RRAM array serves as both the storage medium for intermediate data and the computational element for pooling operations, eliminating the need for separate data transmission between processor and memory.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The RRAM-based max pooling operation modules perform computation autonomously on data already stored in the RRAM array, without requiring constant intervention from external processors. This self-service capability allows the system to perform pooling operations in-place, significantly reducing the energy associated with data movement.

Inventive Principle:
Principle #25Self-service

3Ease of operation

If intermediate calculation data in convolutional layers and pooling layers is stored and re-read using conventional memory, then computation can proceed, but a large amount of data transmission occurs between storage and computation

Engineering Contradiction:
Improvedata storage and retrievalVSAvoiddata transmission volume
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent segments the neural network processing into distinct functional modules, with RRAM-based max pooling operation modules handling pooling operations independently. This segmentation allows intermediate data to be processed locally within the RRAM array rather than being continuously transferred to external memory and back.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a traditional von Neumann architecture with separate computation and storage dimensions to a more integrated architecture where computation occurs within the storage medium itself. The RRAM array enables in-memory computing for pooling operations, effectively adding a computational dimension to the storage space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution significantly reduces storage consumption and energy consumption by integrating pooling calculation and storage, thereby shortening calculation time and minimizing data interaction.

Implementation Method 1

control the current flowing through the RRAM by the gate voltage of the transistor of the 1T1R memory to regulate the conductance value of the RRAM

Methodology Applied
Scientific EffectConductance regulation: Electrical Resistance

Implementation Method 2

utilizes the non-volatile multi-valued conductance regulation characteristic of RRAM

Methodology Applied
Scientific EffectNon-volatile multi-valued conductance: Electrical Resistance

Data Source

PatentUS11416744B2Max pooling processor based on 1T1R memory
Publication Date: 2022.08.16 HUAZHONG UNIV OF SCI & TECH
  • US11416744B2 patent drawing
  • US11416744B2 patent drawing
  • US11416744B2 patent drawing

AI summary

The present disclosure belongs to the technical field of artificial neural networks, and provides to a max pooling processor based on 1T1R memory, comprising an input module, a max pooling operation module, and an output module; the input module is configured to transmit an operating voltage according to the convolution result in the convolutional neural network; the 1T1R memory in the max pooling operation module is configured to adjust a conductance value of the RRAM according to the gate voltage of the transistor therein to achieve the max pooling operation by using the non-volatile multi-value conductance regulation characteristic of the RRAM, and store a max pooling result; and the output module is configured to read the max pooling result and output it.