1T1R Resistive Memory Cell With Vertical Transistor and Buried Bit Line
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Solution Overview
Problem
Current semiconductor memory technologies, such as Flash and DRAM, face scaling limitations beyond 18 nm, and existing resistive memory devices like RRAM have complex fabrication processes and non-uniform gate oxides, which hinder scalability and memory cell packing density.
Innovation Solution
A 1T1R resistive memory cell with a vertical transistor built in a silicon pillar and a buried bit line, fabricated using a self-aligned process that divides the active area into pillar-shaped sub-regions, reducing complexity and area occupancy to 4F2, thereby enhancing scalability and packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pillar diode structure with tunnel gate surface effect transistor is used, then resistive switching function is achieved, but gate oxide non-uniformity occurs and diode function is lost
Solution Approach 1:
The invention divides the active area into four pillar-shaped sub-regions using isolation trenches, with each sub-region containing a vertical transistor. This segmentation approach creates uniform gate oxide structures while maintaining the resistive switching function through controlled division of the memory cell structure.
Solution Approach 2:
The invention transitions from a planar transistor structure to a vertical transistor structure built in pillar-shaped sub-regions. This dimensional change enables uniform gate oxide formation while achieving the required resistive switching functionality through the vertical channel architecture.
2Ease of operation
If FET access resistive memory array is used, then lower operating voltage and better current control are achieved, but fabrication process complexity increases
Solution Approach 1:
The invention merges the bit line and word line into a single trench structure, with the bit line trench extending deeper than the word line trench. This merging approach simplifies the fabrication process by reducing the number of separate trench formation steps while maintaining FET access functionality with improved current control.
Solution Approach 2:
The vertical transistor structure serves multiple functions: it provides FET access for low-voltage operation and current control, while the integrated bit line and word line trenches reduce fabrication complexity. The unified structure achieves both operational excellence and manufacturing simplicity.
3Ease of operation
If conventional memory cell layout is used, then standard connectivity is achieved, but area occupancy increases and packing density decreases
Solution Approach 1:
The invention nests the word line trench within the bit line trench structure, with the word line trench being shallower and positioned within the deeper bit line trench. This nested arrangement allows both bit line and word line connectivity while minimizing the overall area occupied by the memory cell, achieving high packing density.
Solution Approach 2:
The invention utilizes vertical dimensionality by creating trenches at different depths within the substrate. The bit line trench extends deeper than the word line trench, enabling three-dimensional routing that reduces planar area occupancy while maintaining standard connectivity functionality.
Data Source
AI summary
A memory structure includes an active area surrounded by first isolation trenches and second isolation trenches; a bit line trench recessed into the active area of the semiconductor substrate; a word line trench recessed into the active area of the semiconductor substrate and being shallower than the bit line trench. The bit line trench and the word line trench together divide the active area into four pillar-shaped sub-regions. A bit line is embedded in the bit line trench. A word line is embedded in the word line trench. A vertical transistor is built in each of the pillar-shaped sub-regions. A resistive memory element is electrically coupled to the vertical transistor.