1T2R ReRAM Cell Programming Window and Endurance via Preliminary Action
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Solution Overview
Problem
One-transistor two-resistor (1T2R) ReRAM cells face challenges in endurance and reliability due to leak paths and a small programming window, which limits their effectiveness compared to other ReRAM configurations, while also incurring an area penalty.
Innovation Solution
A semiconductor ReRAM device with a one-transistor two-resistor configuration where the first resistor is reset to a high resistive value before the second resistor is set to a low resistive value, allowing for differential read operations and increased endurance without the need for additional transistors, thus optimizing area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a 1T2R configuration is used, then the area is reduced compared to 2T2R, but the endurance and reliability are degraded due to leak paths and small programming window
Solution Approach 1:
The patent applies preliminary action by resetting the first resistor to a high resistive state before setting the second resistor to a low resistive state during write operations. This sequential approach ensures that leak paths are eliminated before programming, preventing interference between the two resistors and improving both endurance and reliability while maintaining the compact 1T2R structure
Solution Approach 2:
The patent implements dynamic operation by alternating between reading and writing modes, and between resetting and setting resistors. The system dynamically switches between different operational states (read/write, reset/set) to optimize performance, allowing the 1T2R cell to achieve reliable operation through temporal separation of conflicting operations
2Speed
If aggressive programming is used to overcome small programming window, then the programming speed is improved, but the endurance is reduced
Solution Approach 1:
The patent uses preliminary action by resetting the first resistor before setting the second resistor. This preparatory step creates a high-resistance state that isolates the bit line from unwanted current paths, enabling gentler programming conditions that improve endurance while maintaining adequate programming speed through the controlled sequence
Solution Approach 2:
The patent employs periodic action through alternating read and write operations, and through the cyclic process of resetting and setting resistors. This periodic operation allows the cell to recover between aggressive programming events, distributing stress over time and improving overall endurance while maintaining programming effectiveness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the programming window and endurance of 1T2R ReRAM cells, reducing reading errors and maintaining reliability without the area penalties associated with additional transistors, allowing for efficient writing and reading operations.
Implementation Method 1
The process of operation of the ReRAM cell includes the forming of the cell. This typically requires creating a filament which thereafter may be reset, or broken, for the purpose of creating a high resistance, or set, in fact reformed so that low resistance is achieved.
Data Source
AI summary
A semiconductor resistive random-access memory (ReRAM) device of an array including at least one ReRAM cell is provided. The ReRAM cell includes a word line; a select line; a first bit line; a second bit line having a polarity opposite of that of the first bit line; a first resistor having a first terminal and a second terminal, wherein the second terminal of the first resistor is connected to the first bit line; a second resistor having a first terminal and a second terminal, the second terminal of the second resistor is connected to the second bit line; and a transistor having a gate terminal, a source terminal and a drain terminal; the word line is connected to the gate terminal, the select line connected to the source terminal, and the drain terminal connected to the first terminal of the first resistor and the first terminal of the second resistor.