1TNC Ferroelectric Memory Bit-Cell Pulsing Scheme
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ferroelectric memory bit-cells suffer from charge degradation and disturbance due to parasitic capacitance and leakage, especially when the plate-line is parallel to the bit-line, leading to unreliable data retention and increased power consumption.
Innovation Solution
Implementing a pulsing scheme that involves word-line boosting and specific pulse patterns on the bit-line and plate-line during write and read operations, along with the use of low leakage transistors and higher dielectric constant materials, to mitigate disturb voltage and reduce parasitic capacitance effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the plate-line is parallel to the bit-line in 1TNC ferroelectric memory bit-cell, then the memory density and area utilization are improved, but charge degradation and disturbance occur due to parasitic capacitance and leakage
Solution Approach 1:
The patent implements a pulsing scheme that applies periodic voltage pulses to the word-line and plate-line during read and write operations. This periodic action allows precise control of the voltage across ferroelectric capacitors, enabling data retrieval while minimizing charge disturbance and leakage effects, thus resolving the contradiction between area utilization and data retention reliability
Solution Approach 2:
The patent changes the voltage parameters dynamically by applying boosted voltages to the word-line and controlled voltage pulses to the plate-line. This parameter change approach enables the system to maintain low leakage states during idle periods while achieving sufficient voltage levels during active operations, resolving the contradiction between compact layout and charge stability
2Area of stationary object
If the plate-line is parallel to the bit-line, then the memory cell size is reduced, but power consumption increases due to leakage and disturbance voltage
Solution Approach 1:
The pulsing scheme applies voltage pulses only during active read/write operations rather than maintaining continuous voltage levels. This periodic action reduces leakage current and power consumption while still achieving the necessary voltage levels for reliable data retrieval in the compact parallel plate-line configuration
Solution Approach 2:
The patent applies preliminary voltage boosting to the word-line before activating the plate-line during write operations. This preliminary action ensures that the ferroelectric capacitor is properly prepared and reduces the overall energy required for the write operation, addressing the power consumption issue in compact memory cell designs
3Ease of operation
If standard read/write operations are used without pulsing scheme, then the operation simplicity is maintained, but charge disturbance and read disturb effects increase
Solution Approach 1:
The pulsing scheme introduces periodic voltage pulses to the word-line and plate-line that are synchronized with the read/write operation timing. This periodic action provides precise control over when voltage is applied, minimizing charge disturbance to non-selected cells while maintaining relatively simple operation sequences that can be integrated into existing memory controllers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively minimizes charge disturbance, enhances data retention, and reduces power consumption by controlling the voltage across ferroelectric capacitors, thereby improving the reliability and endurance of ferroelectric memory bit-cells.
Implementation Method 1
The memory comprises a plurality of memory bit-cells, each bit-cell including a ferroelectric capacitor
Implementation Method 2
Ferroelectric memory bit-cells suffer from charge degradation and disturbance due to parasitic capacitance and leakage
Data Source
AI summary
A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.