1TnR Resistive Memory Cell Array Architecture
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Solution Overview
Problem
Existing resistive memory arrangements face limitations in terms of space requirements, read-out speed, and interference vulnerabilities, particularly in cross-point and 1T1R configurations.
Innovation Solution
The 1TnR memory cell arrangement connects n cell resistors to a drive element, with control electrodes connected to word lines and bit lines, and second electrodes connected to plate lines, allowing for efficient addressing and minimizing interference, while using diodes and specific voltage methods for writing, reading, and erasing to manage threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If cross-point arrangement is used, then space requirement is reduced, but read-out speed decreases and read-out complexity increases
Solution Approach 1:
The memory array is segmented into multiple independently controllable blocks, each with its own drive elements and plate lines. This allows parallel read-out operations from different blocks simultaneously, increasing overall read-out speed while maintaining the compact cross-point structure.
Solution Approach 2:
The patent introduces a third dimension of control through multiple plate lines connected to different electrodes of the drive elements. This additional control dimension enables selective activation of specific memory cells within each block, allowing fast random access without increasing the two-dimensional footprint of the memory array.
2Speed
If 1T1R arrangement is used, then read-out speed improves, but space requirement increases
Solution Approach 1:
Multiple memory cells sharing common bit lines and word lines are merged into functional blocks controlled by a single drive element. This consolidation reduces the number of drive elements needed compared to traditional 1T1R arrangements, decreasing the space requirement while maintaining fast read-out capabilities through the additional plate line control dimension.
3Area of stationary object
If cross-point arrangement is used, then space requirement is reduced, but read-out complexity increases
Solution Approach 1:
The memory array is divided into multiple blocks with independent drive elements and plate lines. This segmentation simplifies the read-out process by allowing selective activation of specific blocks, reducing the complexity of addressing and read-out operations compared to a monolithic cross-point array while maintaining compact spacing.
Solution Approach 2:
The plate lines serve as intermediary control elements between the drive elements and the memory cells. This intermediary layer simplifies the read-out complexity by providing an additional control dimension that enables selective cell access without requiring complex decoding logic, thus reducing read-out complexity while maintaining the compact cross-point structure.
4Adaptability or versatility
If MRAM arrangement with write line is used, then writing capability is achieved, but read-out speed decreases due to two read cycles
Solution Approach 1:
The plate lines serve multiple functions: they control the drive elements for both read and write operations, and they provide direct access to memory cells for fast read-out. This multi-functionality eliminates the need for separate write lines and multiple read cycles, enabling both writing capability and fast single-cycle read-out in the same architecture.
Data Source
AI summary
Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.