1xN Compiler Closed-Loop DFM for VLSI Cell Optimization
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Solution Overview
Problem
Current integrated circuit design methodologies employ an open-loop process that separates logic capture and physical realization, leading to lost optimizations and inefficiencies in design improvements, particularly in reducing power consumption and increasing performance, due to the lack of coherence and manual intervention required for physical optimizations before reaching the logic-freeze stage.
Innovation Solution
A closed-loop 1×N compiler is used to detect relationships between adjacent cells of 1×N building blocks, applying design-for-manufacturing (DFM) alterations such as adding polysilicon, metal, merging diffusion areas, and enhancing implant coverage to optimize physical design representations, enabling automated maintenance of physical optimizations throughout the design flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an open-loop design process is used to separate logic capture and physical realization, then the design process becomes simpler and more modular, but physical optimizations are lost and design improvements cannot be maintained across iterations
Solution Approach 1:
The patent implements a closed-loop design process where physical design information is fed back to the logic design stage. The compiler continuously monitors physical optimizations and feeds this information back to maintain and refine logic designs, ensuring that physical optimizations are preserved across iterations rather than lost in open-loop processes.
Solution Approach 2:
The system enables automated maintenance of physical optimizations through the compiler, which self-manages the coordination between logic and physical design stages. This eliminates the need for manual re-optimization in each iteration, as the system automatically preserves and maintains physical design improvements across design flow iterations.
2Reliability
If manual intervention is used for physical optimizations, then design improvements can be maintained, but considerable time is spent on constant updating and optimization
Solution Approach 1:
The compiler automatically maintains physical optimizations without requiring manual intervention. The system self-manages the optimization process by continuously monitoring physical design information and automatically updating logic designs to preserve optimizations, eliminating the time-consuming manual updating process while maintaining reliability.
Solution Approach 2:
The patent replaces the manual mechanical process of constant updating and re-optimization with an automated compiler system. This mechanical substitution transforms the labor-intensive manual intervention into an automated computational process, significantly increasing design iteration speed while maintaining the quality of physical optimizations.
3Use of energy by moving object
If designers make adjustments to circuit devices for power optimization, then power consumption is reduced, but these optimizations are lost when logic is re-synthesized in open-loop processes
Solution Approach 1:
The closed-loop compiler feeds back information about power optimizations from the physical design stage to the logic design stage. When designers make power optimization adjustments, the compiler detects these changes and feeds this information back to maintain the optimizations during subsequent logic synthesis iterations, preventing loss of power optimization benefits.
Solution Approach 2:
The system ensures continuous maintenance of power optimizations throughout the design process. Rather than allowing optimizations to be lost between discrete design stages, the compiler continuously preserves and maintains power optimization benefits across all iterations of the design flow, ensuring uninterrupted improvement in power consumption.
4Ease of operation
If specific logic functions are defined with fixed physical realizations, then design clarity is improved, but designers must know details at early stages and manually optimize for power, performance, and area
Solution Approach 1:
The compiler serves multiple functions: it maintains design clarity by preserving fixed physical realizations while simultaneously automating the optimization of power, performance, and area. This multi-functional tool eliminates the need for separate manual optimization processes while maintaining the benefits of specific logic function definitions.
Solution Approach 2:
The system automates the optimization process for power, performance, and area through the compiler, which self-manages these optimizations without requiring manual designer intervention. This reduces the device complexity and effort required while maintaining design clarity through fixed physical realizations.
Data Source
AI summary
Embodiments that make DFM alterations to cells of 1×N building blocks via a closed-loop 1×N compiler are disclosed. Some embodiments comprise using a 1×N compiler to detect a relationship between two adjacent cells of a 1×N building block. Based on the relationship, the embodiments select a DFM alteration and apply the alteration to a physical design representation. The embodiments may apply various types of DFM alterations depending on the relationship, such as adding polysilicon, adding metal to create redundant connections, and merging diffusion areas to increase capacitance on supply nodes. Further embodiments comprise an apparatus having a cell examiner to examine two adjacent cells of a 1×N building block and determine a relationship of the two cells. The apparatus also comprises a DFM selector to select a DFM alteration based on the relationship and a DFM applicator to apply the selected DFM alteration to one of the cells.