2.5D Semiconductor Package Layout for Shorter Power Paths
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Solution Overview
Problem
Conventional semiconductor packages face issues with power transfer efficiency due to long power paths through substrates and interposers, leading to increased manufacturing costs and design limitations when embedding capacitors.
Innovation Solution
A 2.5D semiconductor package design using front-side and back-side redistribution layers with organic and inorganic dielectrics, eliminating the need for embedded capacitors and interposers, and incorporating through-substrate vias to reduce power transfer path length and improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a long power path through board, substrate, and interposer is used to connect PMIC die to semiconductor chips, then the package structure is flexible and manufacturable, but the power transfer efficiency deteriorates due to power loss at nodes
Solution Approach 1:
The patent transitions from a conventional planar power distribution architecture to a three-dimensional stacked architecture. The PMIC die is positioned directly beneath the semiconductor chips in the vertical dimension, creating short vertical power paths through the substrate instead of long horizontal paths through board and interposer layers. This dimensional change dramatically reduces power path length and associated losses.
2Loss of energy
If MIM capacitor or ISC is embedded within the interposer to strengthen power characteristics, then power transfer efficiency improves, but the manufacturing cost increases
Solution Approach 1:
The patent extracts the power management function from the interposer layer and places it in a dedicated PMIC die positioned directly under the chips. This eliminates the need to embed complex MIM capacitors or ISC structures within the interposer, thereby reducing manufacturing complexity and cost while maintaining effective power delivery through the short vertical path.
Solution Approach 2:
The substrate serves as an intermediary structure that directly connects the PMIC die to the semiconductor chips, eliminating the need for additional power compensation components. The substrate's direct vertical connection path provides efficient power transfer without requiring MIM capacitors or ISC, simplifying the overall structure and reducing manufacturing costs.
3Loss of energy
If capacitors are embedded within the substrate to strengthen power characteristics, then power transfer efficiency improves, but the design becomes limited and implementation becomes difficult due to multi-layer structure requirements
Solution Approach 1:
The patent extracts the power management functionality from the substrate structure itself and places it in a separate PMIC die. This eliminates the need to embed capacitors within the substrate's multi-layer structure, avoiding the associated design limitations and manufacturing difficulties while still achieving effective power delivery through the direct vertical connection.
Solution Approach 2:
The substrate acts as a simple intermediary connecting the PMIC die to the chips, without requiring embedded capacitor structures. The direct vertical power path through the substrate provides efficient power transfer, eliminating the need for complex multi-layer capacitor embeddings and their associated design constraints.
4Loss of energy
If an interposer with embedded capacitors is used to compensate for power loss, then power characteristics improve, but the manufacturing cost and device complexity increase
Solution Approach 1:
The patent extracts the power management function from the interposer and places it in a dedicated PMIC die positioned directly under the chips. This eliminates the need for complex interposer structures with embedded MIM capacitors or ISC, reducing both manufacturing cost and device complexity while maintaining effective power delivery through the short vertical path.
Solution Approach 2:
The substrate serves as a simple intermediary structure that directly connects the PMIC die to the semiconductor chips, eliminating the need for complex interposers with embedded capacitors. This direct vertical connection provides efficient power transfer while significantly reducing structural complexity and manufacturing cost.
Data Source
AI summary
A semiconductor package includes a first redistribution layer, a logic die on the first redistribution layer, a high bandwidth memory on the first redistribution layer and next to the logic die, a frame on the first redistribution layer, next to the logic die, and next to the high bandwidth memory, a molding material covering the logic die, the high bandwidth memory, and the frame, on the first redistribution layer, and a second redistribution layer on the molding material, where the second redistribution layer electrically connects the logic die to the high bandwidth memory.