2.5D Interposer Package Layout for Warpage-Controlled Bonding
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Solution Overview
Problem
The warpage differences between molded interposer packages (MIP) and package substrates due to varying coefficients of thermal expansion (CTEs) lead to poor bonding and compromised electrical characteristics in 2.5D packages.
Innovation Solution
The 2.5D package design includes an interposer with semiconductor chips, an underfill member, and a mold that reduces the amount of mold material in certain spaces, allowing for improved alignment and bonding with the package substrate during thermal compression bonding (TCB), enhancing electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a mold is formed over the semiconductor chips and interposer, then the chips are protected and the package structure is complete, but the warpage difference between the MIP and package substrate increases due to varying CTEs
Solution Approach 1:
The patent applies local quality by forming the mold selectively only in regions where chips are present, while leaving gaps in regions without chips. This creates non-uniform mold distribution that locally compensates for warpage in chip regions while maintaining overall package integrity. The mold is formed to a first thickness in chip regions and a second thickness (lower than the first) in gap regions, addressing warpage locally rather than uniformly across the entire package.
Solution Approach 2:
The patent changes the physical parameters of the mold by controlling its thickness variation across different regions. The mold thickness is specifically designed to be greater in regions with chips and lesser in gap regions, creating a graded structure that compensates for thermal expansion differences. This parameter change in mold thickness directly addresses the warpage issue caused by varying CTEs between materials.
2Manufacturing precision
If the mold volume is reduced to decrease warpage difference, then bonding quality improves, but the protective coverage and structural integrity may be compromised
Solution Approach 1:
The patent implements local quality by varying the mold thickness according to the local structural requirements. In regions with chips, the mold maintains a greater thickness (first thickness) to provide adequate protection and support. In gap regions between chips, the mold thickness is reduced (second thickness) to minimize warpage. This localized differentiation allows the package to maintain both bonding precision and structural integrity simultaneously.
Solution Approach 2:
The patent applies partial action by forming the mold only in necessary regions rather than uniformly across the entire package surface. The mold is selectively formed to cover chip regions adequately while reducing coverage in gap regions. This partial mold formation is sufficient to protect the critical chip areas and ensure bonding alignment, while avoiding the excessive mold volume that would cause warpage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced warpage difference between the MIP and package substrate results in enhanced electrical characteristics and improved bonding, ensuring stable electrical connections.
Implementation Method 1
Degrees of warpages of the MIP and the package substrate are different from each other according to coefficients of thermal expansion (CTEs)
Implementation Method 2
The MIP may be bonded onto the package substrate by a thermal compression bonding (TCB) process
Data Source
AI summary
A 2.5D package includes an interposer, semiconductor chips on the interposer, an underfill member that is between the interposer and each of the semiconductor chips and between the interposer and an uppermost surface of one or more semiconductor chips of the semiconductor chips, and a mold on the interposer and a first sidewall of the one or more semiconductor chips, where the semiconductor chips define one or more recesses that are on the underfill member and at least partially expose a second sidewall of the one or more semiconductor chips, and where the second sidewall of the one or more semiconductor chips is opposite to the first sidewall of the one or more semiconductor chips.