25% Duty-Cycle LO Clock Circuit With 90° Phase-Shifted Inputs
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Solution Overview
Problem
Existing local oscillator clock generation circuits face challenges in reducing power consumption and improving noise performance, particularly in generating stable frequencies with low harmonics while accounting for temperature, voltage, and mechanical drift, and require duty cycles other than the standard 50% to prevent signal crossover in RF/microwave applications.
Innovation Solution
A clock generation circuit and method that utilize NAND gates with specific NMOS and PMOS transistor configurations to generate 25% duty cycle local oscillator clocks from 50% duty cycle clocks, with the second clock lagging the first clock by 90 degrees in phase, allowing for reduced power consumption and improved noise performance by eliminating the need for pull-up PMOS transistors for the lagging clock, thus minimizing short circuit current and load on the local oscillator clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock generation circuits are used to generate stable frequency, then frequency stability is improved, but power consumption increases
Solution Approach 1:
The patent extracts and eliminates the pull-up PMOS transistor from the clock generation circuit for the lagging clock signal. By removing this component, the circuit achieves reduced power consumption while maintaining frequency stability through the remaining pull-down path and the inherent properties of the 90-degree phase-shifted clock signals.
2Object-affected harmful factors
If duty cycle is changed from 50% to 25%, then signal crossover is prevented in RF applications, but circuit complexity increases
Solution Approach 1:
The patent applies asymmetry by treating the two clock signals differently: one clock signal includes a pull-up path while the other (lagging by 90 degrees) excludes it. This asymmetric configuration enables the generation of 25% duty cycle signals that prevent signal crossover in RF applications while keeping the circuit relatively simple.
3Power
If pull-up PMOS transistors are included for both clocks, then output power is sufficient, but short circuit current increases
Solution Approach 1:
The patent converts the potential harm of having insufficient output power into a benefit by strategically placing pull-up paths only where needed. By providing pull-up paths only for the leading clock signal and relying on the pull-down path for the lagging clock, the circuit achieves adequate output power while eliminating the harmful short circuit current that would result from having pull-up paths for both clocks.
Data Source
AI summary
In certain aspects, a clock generation circuit couples to a first clock having a first duty cycle and a second clock having the first duty cycle. The second clock lags the first clock by 90 degrees in phase. The clock generation circuit is configured to couple the output terminal to a ground when the first clock and the second clock both are at logic high and decouple the output terminal from the ground when at least one of the first clock and the second clock is at logic low and couple a supply voltage to the output terminal only when the first clock is at logic low and decouple the supply voltage from the output terminal when the first clock is at logic high. The clock generation circuit generates clock signals having a second duty cycle.