256-Bit ECC Calibration for Two-Bit Error Correction

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Solution Overview

Problem

Existing ECC technologies can detect but not correct two-bit errors in data transmission, affecting system stability, especially when transferring 256 bits.

Innovation Solution

A two-bit error calibration device and method that divides data into 32 data sets, calculates checksums and bit sums, and uses calibration chips to identify and correct errors by comparing received data with stored calibration bits, minimizing operational bits and maintaining transmission quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ECC checking is used for data transmission, then data error detection and correction capability is improved, but the amount of data to be transmitted increases

Engineering Contradiction:

Improvedata error correction capabilityVSAvoidamount of data to be transmitted

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent divides 256-bit data into 32 data sets of 8 bits each, and introduces 32 calibration bits (one for each data set). This segmentation approach allows targeted error correction for two-bit errors within each data set without requiring extensive additional transmission bits, thus resolving the contradiction between error correction capability and data transmission volume.

Inventive Principle:

Principle #1Segmentation

2Reliability

If two-bit error correction is implemented, then system stability is improved, but the complexity of the correction system increases

Engineering Contradiction:

Improvesystem stabilityVSAvoidcorrection system complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces calibration bits as intermediary elements that facilitate two-bit error correction. These calibration bits serve as mediators between the transmitted data and the error correction process, enabling the system to identify and correct two-bit errors without requiring complex correction mechanisms, thus improving system stability while controlling system complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If minimal additional data is used for error checking, then transmission quality is maintained, but the error detection and correction capability is reduced

Engineering Contradiction:

Improveerror detection and correction capabilityVSAvoidadditional data for error checking

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent changes the parameter structure by organizing 256-bit data into 32 groups of 8 bits and introducing 32 calibration bits (one per group). This parameter change enables the system to detect and correct two-bit errors using minimal additional data, maintaining transmission quality while enhancing error correction capability through optimized data structure and calibration bit utilization.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10516504B2Two bit error calibration device for 256 bit transfer and the method for performing the same

Publication Date: 2019.12.24 CHANG CHIN PEN

AI summary

A method for determining two bits errors in transmission of 256 bits and the device for realization of this method is provided. By the method and device, the two error bits transferred bits can be determined and corrected by using least bits in operation. Therefore, the amount of data in transmission is increased with a least quantity and thus the transmission quality is not affected.