2D Cache Latch Page Buffer for NAND Flash Memory
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Solution Overview
Problem
Current NAND flash memory devices face challenges in reducing size, increasing data input and output speeds, and efficiently repairing defects, particularly due to limitations in the configuration and arrangement of page buffers.
Innovation Solution
The memory device incorporates a page buffer with a two-dimensional arrangement of cache latches in both column and row directions, allowing for efficient data exchange and defect repair by redistributing cache latches across multiple stages, reducing the device's size and enhancing data output speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache latches are arranged in a conventional one-dimensional configuration, then the page buffer structure is simple, but the memory device size is larger and data output speed is slower
Solution Approach 1:
The patent applies two-dimensional arrangement of cache latches in both row and column directions, transforming the conventional one-dimensional linear arrangement into a matrix structure. This dimensional change enables parallel data paths and reduces the critical path length for data output, thereby increasing data output speed while utilizing the memory device area more efficiently
2Productivity
If cache latches are arranged in a two-dimensional configuration, then data input and output speeds increase, but the arrangement complexity increases
Solution Approach 1:
The patent segments the cache latch array into multiple independent row units and column units that can be selectively activated. Each row and column can be independently controlled through select signals, allowing the system to activate only the necessary segments for current operations. This segmentation reduces the effective complexity by breaking down the large two-dimensional array into manageable, independently controllable blocks
3Ease of repair
If cache latches are concentrated in a single location, then the page buffer configuration is simple, but defect repair efficiency is lower
Solution Approach 1:
The patent divides the cache latch array into multiple row units and column units that are spatially distributed across the memory device. This segmentation allows defective rows or columns to be independently identified and repaired without affecting the entire cache latch system. The distributed arrangement enables localized repair operations, significantly improving defect repair efficiency compared to a concentrated single-location configuration
Data Source
AI summary
A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.