Two-Dimensional Cache Addressing for Multi-Dimensional Data Access
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Solution Overview
Problem
Current cache memory systems are inefficient when processing multi-dimensional data structures like images or matrices, as they rely on linear addressing, leading to slow and inefficient access to data that does not fit well in this linear arrangement.
Innovation Solution
A cache system is designed with a p x q array of memory units, each containing an m x n array of memory cells, and equipped with row and column addressing units that use multiplexers to allow for parallel reading and writing of multiple rows and columns, enabling non-linear access to multi-dimensional data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If linear addressing is used in cache memory, then the cache structure is simple and easy to implement, but access efficiency to multi-dimensional data structures deteriorates
Solution Approach 1:
The patent transforms the traditional one-dimensional linear address space into a two-dimensional address space with row and column dimensions. This allows data to be accessed along multiple directions (horizontal and vertical) simultaneously, matching the spatial locality patterns of multi-dimensional data structures like images and matrices, thereby resolving the contradiction between structural simplicity and access efficiency.
Solution Approach 2:
The cache address space is segmented into row addresses and column addresses independently. The row addressing unit and column addressing unit can operate separately and in parallel, allowing the cache to service multiple access requests simultaneously. This segmentation maintains implementation simplicity while dramatically improving access efficiency for spatially localized data patterns.
2Loss of information
If multiple read operations are required to access scattered data points, then data access completeness is improved, but access time increases
Solution Approach 1:
The patent enables continuous parallel access to multiple data points by maintaining multiple active read ports (row and column addressing units operating simultaneously). Instead of sequentially completing one read operation before starting another, the system performs multiple reads in parallel, eliminating idle time and ensuring continuous useful action throughout the access process.
Solution Approach 2:
By adding the column dimension to the traditional row-based addressing, the patent creates a two-dimensional access matrix that can simultaneously address data points along both horizontal and vertical directions. This dimensional expansion allows the cache to access scattered data points in a single operation rather than requiring multiple sequential reads, thus reducing access time while maintaining complete data access.
3Device complexity
If traditional linear cache is used, then device complexity is low, but read flexibility for non-linear data patterns deteriorates
Solution Approach 1:
The patent introduces a column addressing dimension alongside the traditional row addressing dimension, creating a two-dimensional addressing space. This dimensional enhancement provides read flexibility for various non-linear data patterns (horizontal lines, vertical lines, scattered points) while maintaining relatively simple addressing logic through independent row and column address generators, thus resolving the contradiction between device complexity and read flexibility.
Solution Approach 2:
The dual addressing system (row and column) provides universal access capability for multiple data access patterns. The same cache structure can efficiently service horizontal accesses, vertical accesses, and scattered point accesses by simply changing which addressing unit (row or column) is activated, making the cache adaptable to various algorithms without requiring separate specialized structures for each access pattern.
Data Source
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AI summary
A cache includes a p-by-q array of memory units; a row addressing unit; and a column addressing unit. Each memory unit has an m-by-n array of memory cells. The column addressing unit has, for each memory unit, m n-to-one multiplexers, one associated with each of the m rows of the memory unit, wherein each n-to-one multiplexer has an input coupled to each of the n memory cells associated with the row associated with that multiplexer. The row addressing unit has, for each memory unit, n m-to-one multiplexers, one associated with each of the n columns of the memory unit, wherein each m-to-one multiplexer has an input coupled to each of the m memory cells associated with the column associated with that multiplexer. The row addressing unit and column addressing unit support reading and/or writing of the array of memory units, e.g. using virtual or physical addresses.