2-D Material Channel Transistor With Air-Gap Gate Dielectric
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, requiring innovative solutions for efficient and reliable device manufacturing.
Innovation Solution
The use of 2-D materials such as graphene and transition metal dichalcogenides in semiconductor devices, including the formation of in-plane gate transistors with air gaps acting as gate dielectrics, and the application of passivation layers to protect the channel layer from contaminants and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but fabrication process difficulty and reliability increase
Solution Approach 1:
The patent changes the material parameter from traditional silicon-based semiconductors to 2-D materials (graphene, transition metal dichalcogenides), which fundamentally alters the electrical and physical properties. This material parameter change enables maintaining device reliability at smaller feature sizes by providing superior carrier mobility and unique two-dimensional electronic structures that are less sensitive to scaling effects
Solution Approach 2:
The patent employs composite material structures combining 2-D material channel layers with various gate dielectric materials (HfO2, Al2O3, SiO2) and metal gates. This composite approach leverages the high mobility of 2-D materials while using conventional dielectrics for gate control, achieving both scalability and reliability in miniaturized devices
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but fabrication process complexity increases
Solution Approach 1:
The patent segments the device structure into distinct functional layers: 2-D material channel layer, gate dielectric layer, and metal gate layer. This segmentation allows each layer to be optimized and fabricated using specialized processes, simplifying the overall fabrication by breaking down the complex miniaturization challenge into manageable modular components
Solution Approach 2:
The patent introduces 2-D materials as an intermediary channel layer between the gate dielectric and source/drain contacts. This intermediary material provides a platform that bridges the gap between conventional semiconductor processes and next-generation device requirements, enabling standard fabrication techniques to be applied while achieving advanced device performance at small scales
3Ease of manufacture
If traditional gate dielectrics are used in miniaturized devices, then manufacturing is simpler, but device performance and mobility are limited
Solution Approach 1:
The patent applies local quality by using different materials for different functional regions: 2-D materials for the channel where high mobility is critical, conventional dielectrics (HfO2, Al2O3) for the gate insulator where electrical control is needed, and metal gates for high-capacitance coupling. Each material is optimized for its specific local function, achieving high performance while maintaining manufacturability
Data Source
AI summary
A semiconductor device includes a substrate. A 2-D material channel layer is over the substrate, in which the 2-D material channel layer includes a channel region and source/drain regions on opposite sides of the channel region. Source/drain metals are over of the source/drain regions of the 2-D material channel layer. A gate metal is over the substrate and non-overlapping the 2-D material channel layer along a vertical direction, in which the gate metal is laterally separated from the 2-D material channel layer by an air gap.