Semiconductor device and method for fabricating the same
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Solution Overview
Problem
Semiconductor devices using two-dimensional (2D) semiconductors face issues with high parasitic capacitance and short channel effects, particularly in miniaturized devices.
Innovation Solution
Incorporation of air spacers and 2D semiconductor materials in the channel layer, along with a flat and coplanar structure to reduce parasitic capacitance and maintain charge mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two-dimensional semiconductors are used as channel materials for miniaturized semiconductor devices, then short channel effects are reduced, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the harmful dielectric material surrounding the gate electrode and replaces it with air spacers, effectively removing the source of parasitic capacitance while preserving the beneficial short channel effect suppression provided by 2D semiconductor channel layers
Solution Approach 2:
The patent employs a composite structure combining 2D semiconductor channel layers with air spacer materials, creating a hybrid architecture that leverages the electrical properties of 2D semiconductors while eliminating parasitic capacitance through air isolation
2Length of moving object
If the channel layer length is greatly reduced for miniaturization, then device size is reduced, but short channel effects increase such as large leakage current and low threshold voltage
Solution Approach 1:
The patent utilizes thin 2D semiconductor films as channel layers that maintain effective channel length control even in miniaturized devices, where the atomic-layer thickness provides superior electrical confinement compared to bulk materials
Solution Approach 2:
The patent changes the material parameter from conventional bulk semiconductor to two-dimensional semiconductor, fundamentally altering the electrical characteristics to suppress short channel effects while enabling further miniaturization
Data Source
AI summary
A semiconductor device and a method for fabricating the semiconductor device are provided. The semiconductor device includes a plurality of device units. The device units includes a first device unit, and the first device unit includes a substrate including two source/drain regions and a gate region disposed between the two source/drain regions; a gate electrode layer disposed on the gate region, and a top surface of the gate electrode layer is coplanar to top surfaces of the two source/drain regions; a first channel layer disposed on the gate electrode layer, wherein the first channel layer includes a 2D semiconductor material; two air spacers disposed below the first channel layer and between the gate region and the two source/drain regions, respectively.