2D Semiconductor Channel With Graphene Contacts for Thin-Channel Scaling
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Solution Overview
Problem
As semiconductor devices are miniaturized, they face performance degradation due to reduced channel thickness, leading to increased mobility and threshold voltage distribution, limiting further size reduction.
Innovation Solution
A semiconductor device utilizing a two-dimensional (2D) material layer with a polycrystalline structure and graphene layers, where the 2D material layer includes a sheet member and protrusions, and graphene layers cover parts of the sheet member and protrusions, reducing contact resistance and overcoming short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of semiconductor device is reduced, then the number of integrated devices and driving speed increase, but performance degradation occurs due to decreased channel thickness
Solution Approach 1:
The patent changes the material parameter from conventional bulk semiconductor to two-dimensional semiconductor material, which maintains excellent electrical properties even at atomic-scale thickness (single layer or few layers), thereby resolving the performance degradation issue while enabling further miniaturization
Solution Approach 2:
The patent uses composite structure combining two-dimensional semiconductor material with graphene layers and conventional semiconductor layers, creating a hybrid device that leverages the advantages of both 2D materials (atomic thickness, high mobility) and conventional materials (成熟的制造工艺, good interface properties)
2Length of moving object
If the channel thickness is decreased, then device miniaturization is achieved, but mobility and threshold voltage distribution increase
Solution Approach 1:
The patent transitions from three-dimensional bulk semiconductor to two-dimensional semiconductor material, changing the dimensional parameter from 3D to 2D. This maintains a well-defined thickness (single atomic layer or few layers) while preserving excellent electrical properties and reducing variability in mobility and threshold voltage
Solution Approach 2:
The patent employs chemical vapor deposition (CVD) process to grow two-dimensional semiconductor material and graphene layers with atomic-level precision, using gas-phase reactions to achieve controlled thin film formation with uniform thickness and excellent crystalline quality
3Reliability
If two-dimensional material is used to maintain performance at thin thickness, then contact resistance and short channel effects are reduced, but device complexity increases
Solution Approach 1:
The patent utilizes the self-aligned nature of two-dimensional material growth where the 2D semiconductor material and graphene layers grow conformally on the substrate and existing structures, automatically forming aligned interfaces without requiring additional alignment steps, thereby reducing process complexity despite the advanced material system
Solution Approach 2:
The patent introduces graphene layers as an intermediary material between the two-dimensional semiconductor channel and the source/drain electrodes, serving as a buffer that reduces contact resistance and facilitates carrier transport while maintaining the simplicity of the overall device structure
Data Source
AI summary
A semiconductor device may include a two-dimensional (2D) material layer, a source electrode and a drain electrode spaced apart from each other on the 2D material layer, a gate insulating layer and a gate electrode on the 2D material layer between the source electrode and the drain electrode, and graphene layers on both sides of the gate insulating layer. The 2D material layer may include a 2D semiconductor material having a polycrystalline structure. The 2D material layer may include a sheet member and a protrusion. The sheet member may extend along one plane. The protrusion may extend in one direction perpendicular to the one plane. The graphene layer may cover a part of the sheet member and the protrusion.