2D Channel Gate Stack Surface Prep for Uniform High-K Deposition
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Solution Overview
Problem
The challenge lies in uniformly depositing a high-K dielectric layer on a two-dimensional transition metal dichalcogenide channel layer without causing surface damage or oxidation, which is essential for next-generation transistors but is hindered by defects and reactive groups on the surface.
Innovation Solution
A method involving alternately stacking sacrificial semiconductor layers and channel layers on a substrate, forming source and drain regions, and performing a plasma treatment with boron trichloride (BCl3) or other boron-based gases to create a suitable surface for uniform high-K dielectric layer deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If surface treatment methods are applied to enable uniform deposition of high-K dielectric layer, then deposition uniformity is improved, but off-current increases due to surface damage and oxidation
Solution Approach 1:
The patent introduces an intermediary plasma treatment process using BCl3 gas between channel layer formation and high-K dielectric deposition. This plasma treatment modifies the channel layer surface to create optimal conditions for uniform dielectric deposition without causing damage or oxidation, thus serving as a beneficial mediator that resolves the contradiction between deposition uniformity and device reliability
Solution Approach 2:
The patent changes the surface parameters of the channel layer through controlled plasma treatment with BCl3 gas. This treatment modifies surface chemistry and morphology parameters to achieve optimal deposition characteristics while maintaining surface integrity, thereby improving deposition uniformity without increasing off-current
2Manufacturing precision
If plasma treatment is performed on channel layers to prepare surface for deposition, then deposition quality is improved, but surface damage may occur
Solution Approach 1:
The patent carefully controls plasma treatment parameters including gas composition (BCl3), pressure, power, and treatment duration to achieve surface modification that enhances deposition quality while avoiding excessive energy input that could cause damage. The parameter optimization ensures beneficial surface preparation without harmful effects
Solution Approach 2:
The BCl3 plasma acts as an intermediary treatment that prepares the channel layer surface for high-K dielectric deposition. It modifies surface properties to improve deposition quality while the controlled nature of the treatment prevents surface damage, serving as a protective preparatory step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable and uniform deposition of high-K dielectric layers on 2D channel layers, improving the integration circuit's performance by minimizing surface damage and ensuring effective electrical properties.
Implementation Method 1
performing a plasma treatment of boron trichloride (BCL3) on the channel layers
Implementation Method 2
uniformly deposit a high-K dielectric layer on the channel layer through an atomic layer deposition (ALD) process
Data Source
AI summary
A method of manufacturing an integrated circuit device includes alternately stacking sacrificial semiconductor layers and channel layers on a substrate to form a stack structure, forming source regions and drain regions on both sides of the stack structure, forming a gate space between the channel layers by removing the sacrificial semiconductor layers, forming the channel layers to be spaced apart from each other in a perpendicular direction to the substrate, performing a plasma treatment of boron trichloride (BCL3) on the channel layers, forming gate dielectric layers on the channel layers on which the plasma treatment of boron trichloride (BCL3) is performed, and forming gate layers covering the gate dielectric layers in the gate space.