2D Material Channel Stacking for Low-Temperature 3D IC Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Monolithic 3D IC technology faces challenges in forming upper layer devices without damaging lower layer devices due to high thermal budget requirements, limiting the density and performance of integrated circuits.
Innovation Solution
Incorporating a 2D material layer as a channel layer in semiconductor devices using low thermal budget processes, allowing for the formation of 3D stacked semiconductor devices like FinFETs and GAA transistors without degrading existing layers, utilizing materials such as graphene, hexagonal boron nitride, and molybdenum sulfide, which provide high mobility and electrostatic control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high thermal budget processes are used to form upper layer devices, then device performance is improved, but lower layer devices are damaged
Solution Approach 1:
The patent changes the thermal budget parameter from high to low by using low thermal budget processes (annealing temperatures below 400°C) to form upper layer devices, thereby preventing thermal damage to lower layer devices while still achieving functional device formation
Solution Approach 2:
The patent introduces an intermediate dielectric layer between upper and lower layer devices that acts as a thermal barrier, mediating the thermal interaction and protecting lower layers from damage during upper layer fabrication processes
2Adaptability or versatility
If 3D stacking is implemented to increase density, then integration capability is improved, but process complexity increases
Solution Approach 1:
The patent segments the fabrication process into distinct low thermal budget stages for forming different device layers, allowing independent optimization of each layer's formation process and simplifying the overall complex 3D integration fabrication
Solution Approach 2:
The patent transitions from 2D planar integration to 3D vertical stacking, adding the vertical dimension to increase integration density and heterogeneous integration capability while managing process complexity through staged fabrication
3Ease of manufacture
If conventional semiconductor materials are used, then manufacturing experience is leveraged, but thermal budget flexibility is limited
Solution Approach 1:
The patent employs composite material structures including 2D materials (graphene, MoS2), III-V semiconductors, and dielectric materials combined in multi-layer configurations, enabling low thermal budget processing while maintaining manufacturing feasibility through adapted conventional techniques
Data Source
AI summary
In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.