2D Semiconductor Channel Structure for Nanoscale Mobility
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Solution Overview
Problem
There is a limit to reducing the size of transistors with a flat structure, such as MOSFETs, and existing technologies face challenges in achieving high performance and small size due to reduced carrier number and mobility in thin silicon FinFETs.
Innovation Solution
The use of a semiconductor device with a two-dimensional semiconductor material as a channel layer, including graphene, black phosphorus, or transition metal dichalcogenides, in conjunction with a gate electrode and dielectric structure that enhances electrical conductivity and mobility, even at nanoscale thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of transistors is reduced, then more semiconductor devices can be obtained from one wafer and driving speed increases, but the carrier number and mobility decrease
Solution Approach 1:
The patent changes the material parameter from conventional silicon to two-dimensional semiconductor materials (such as MoS2, WS2, WSe2), which maintain high carrier mobility even at reduced thickness. This material substitution allows the transistor to achieve both small size and high performance by fundamentally altering the physical properties of the channel layer.
Solution Approach 2:
The patent transitions from three-dimensional bulk silicon to two-dimensional semiconductor materials, utilizing the dimensional reduction to maintain effective channel control at nanoscale thicknesses. This dimensional change enables continued scaling while preserving carrier mobility through the unique electronic structure of 2D materials.
2Length of moving object
If the channel thickness is reduced to achieve fine sizes, then device miniaturization is achieved, but contact resistance increases and performance deteriorates
Solution Approach 1:
The patent changes the material composition of the channel layer to two-dimensional semiconductors, which inherently maintain high carrier mobility and low contact resistance even at atomic-layer thicknesses. This material parameter change resolves the contradiction between thinness and electrical performance.
Solution Approach 2:
The patent employs composite structures combining two-dimensional semiconductor channel layers with carefully engineered source and drain electrodes, creating optimized interfaces that minimize contact resistance. The composite approach includes potential use of dipole layers or specific electrode materials to enhance contact properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains high electron mobility and enables the creation of high-performance semiconductor devices with fine sizes, such as FinFETs, by reducing contact resistance and improving performance through the gating effect.
Implementation Method 1
improving performance through the gating effect
Implementation Method 2
maintains high electron mobility and enables the creation of high-performance semiconductor devices
Data Source
AI summary
Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.